`include "./m320c50.inc"
module mc50mem (IOD,B0WA,B0RA,WA,RA,NBWR,NBRD,B0D,B1D,B2D,
NSCE,SRNW,SAWA,NSWE,NSOE,SPND,SAPA,SARA,PD_O,SD_O,
NPCE,NPOE,NPWE,PA,CLKRAM);

input  [15:0] IOD;
input  [8:0] B0WA,B0RA,WA,RA;
input  [2:0] NBWR,NBRD;
output  [15:0] B0D, B1D, B2D;

input  [5-1:0] NSCE,SRNW,NSWE,NSOE,SPND;
input  [14:0] SAWA,SAPA,SARA;
output  [15:0] PD_O,SD_O;

input  NPCE,NPOE,NPWE,CLKRAM;
input  [14:0] PA;

wire  [15:0] IOD;
wire  [8:0] B0WA,B0RA,WA,RA;
wire  [2:0] NBWR,NBRD;
wire  [15:0] B0D, B1D, B2D;

wire  [5-1:0] NSCE,SRNW,NSWE,NSOE,SPND;
wire  [14:0] SAWA,SAPA,SARA;
wire  [15:0] q00;
wire  [14:0] address00;
wire  [15:0] data00;
wire  inclock00,outclock00,wren00;

wire  [15:0] q01;
wire  [14:0] address01;
wire  [15:0] data01;
wire  inclock01,outclock01,wren01;

wire  [15:0] q02;
wire  [14:0] address02;
wire  [15:0] data02;
wire  inclock02,outclock02,wren02;

wire  [15:0] q03;
wire  [14:0] address03;
wire  [15:0] data03;
wire  inclock03,outclock03,wren03;

wire  [15:0] q04;
wire  [14:0] address04;
wire  [15:0] data04;
wire  inclock04,outclock04,wren04;

wire  NPCE,NPOE,NPWE,CLKRAM;
wire  [15:0] q;
wire  [14:0] PA;
wire  [14:0] address;
wire  [15:0] data;
wire  inclock,outclock,wren;

wire  [15:0] PD00,SD00,PD01,SD01,PD02,SD02,PD03,SD03,PD04,SD04,PD_PR;
wire   [15:0] PD_O,SD_O;
reg   [15:0] PD_OO0,SD_OO0,PD_OO1,SD_OO1,PD_OO2,SD_OO2,PD_OO3,SD_OO3,PD_OO4,SD_OO4,PD_OO5;
//reg   [15:0] PD_OO,SD_OO;

dprams U1 (IOD,B0WA,B0RA,WA,RA,NBWR,NBRD,B0D,B1D,B2D,CLKRAM);

RAM00_Control U2 (NSCE,SRNW,SAWA,NSWE,NSOE,SPND,SAPA,SARA,IOD,q00,address00,data00,PD00,SD00,wren00);

RAM01_Control U3 (NSCE,SRNW,SAWA,NSWE,NSOE,SPND,SAPA,SARA,IOD,q01,address01,data01,PD01,SD01,wren01);

RAM02_Control U4 (NSCE,SRNW,SAWA,NSWE,NSOE,SPND,SAPA,SARA,IOD,q02,address02,data02,PD02,SD02,wren02);

RAM03_Control U5 (NSCE,SRNW,SAWA,NSWE,NSOE,SPND,SAPA,SARA,IOD,q03,address03,data03,PD03,SD03,wren03);

RAM04_Control U6 (NSCE,SRNW,SAWA,NSWE,NSOE,SPND,SAPA,SARA,IOD,q04,address04,data04,PD04,SD04,wren04);

RAM00 U7 (address00,CLKRAM,data00,wren00,q00);

RAM01 U8 (address01,CLKRAM,data01,wren01,q01);

RAM02 U9 (address02,CLKRAM,data02,wren02,q02);

RAM03 U10 (address03,CLKRAM,data03,wren03,q03);

RAM04 U11 (address04,CLKRAM,data04,wren04,q04);

PrgRAM_Control U12 (NPCE,NPOE,NPWE,PA,IOD,PD_PR,q,address,data,wren);

PrgRAM U13 (address,CLKRAM,data,wren,q);

assign PD_O = PD00;
assign SD_O = SD00;
assign PD_O = PD01;
assign SD_O = SD01;
assign PD_O = PD02;
assign SD_O = SD02;
assign PD_O = PD03;
assign SD_O = SD03;
assign PD_O = PD04;
assign SD_O = SD04;
assign PD_O = PD_PR;

endmodule