//*******************************************************************       ////IMPORTANT NOTICE                                                          ////================                                                          ////Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  ////This file and associated deliverables are the trade secrets,              ////confidential information and copyrighted works of Mentor Graphics         ////Corporation and its licensors and are subject to your license agreement   ////with Mentor Graphics Corporation.                                         ////                                                                          ////These deliverables may be used for the purpose of making silicon for one  ////IC design only.  No further use of these deliverables for the purpose of  ////making silicon from an IC design is permitted without the payment of an   ////additional license fee.  See your license agreement with Mentor Graphics  ////for further details.  If you have further questions please contact        ////Mentor Graphics Customer Support.                                         ////                                                                          ////This Mentor Graphics core (m320c50eng v1999.010) was extracted on         ////workstation hostid 800059c1 Inventra                                      //// ARAU// Copyright Mentor Graphics Corporation and Licensors 1998.// V1.004// m3s016ct// M320C50 Auxillary register arithmetic unit.// Cntrl usage://    0 : Compare AR with ARCR//    1 : Immediate operand//    2 : Subtract operand (1 = subtract)//    3 : Bit reverse (1 = bit reverse)//    4 : Select Input (1 = Index, 0 = '1')//    5 : Select output (1 = Adder, 0 = Input)//// ARAU output://     Cntrl      OpBus//  5 4 3 2 1 0//  0 X X X X X   IpBus//  1 0 0 0 0 0   IpBus+1//  1 0 0 1 0 0   IpBus-1//  1 1 0 0 0 0   IpBus+Index//  1 1 0 1 0 0   IpBus-Index//  1 1 1 0 0 0   IpBus+Index (reverse carry)//  1 1 1 1 0 0   IpBus-Index (reverse carry)//  1 0 0 0 1 0   IpBus+Imm//  1 0 0 1 1 0   IpBus-Imm//  X 0 0 1 0 1   IpBus-ARCR//// The output Z is 1 if the result of the addition/subtraction is zero.// The output C is 1 if the result of the addition overflows or the subtraction// does not overflow.//// Subtraction is performed by inverting the operand and setting the// carry input to the adder high.// Reverse carry propagation is performed by reversing the order of the bits// at the adder inputs and outputs.module m3s016ct (IpBus, Index, ARCR, ShortImm, CBSR1, CBSR2,//*******************************************************************       ////IMPORTANT NOTICE                                                          ////================                                                          ////Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  ////This file and associated deliverables are the trade secrets,              ////confidential information and copyrighted works of Mentor Graphics         ////Corporation and its licensors and are subject to your license agreement   ////with Mentor Graphics Corporation.                                         ////                                                                          ////These deliverables may be used for the purpose of making silicon for one  ////IC design only.  No further use of these deliverables for the purpose of  ////making silicon from an IC design is permitted without the payment of an   ////additional license fee.  See your license agreement with Mentor Graphics  ////for further details.  If you have further questions please contact        ////Mentor Graphics Customer Support.                                         ////                                                                          ////This Mentor Graphics core (m320c50eng v1999.010) was extracted on         ////workstation hostid 800059c1 Inventra                                      //     Cntrl, LdCB1, LdCB2, OpBus, C, Z);    input  [15:0] IpBus, Index, ARCR, CBSR1, CBSR2;    input   [7:0] ShortImm;    input   [5:0] Cntrl;    input         LdCB1, LdCB2;    output [15:0] OpBus;    output        C, Z;    reg  [15:0] OpBus, IpMux, AdderIpA, AdderIpB, IndexRev;    reg         Z;    wire [15:0] AdderOp;    wire        C;    reg [15:0] nBit;// Reverse index bits for reverse carry arithmeticalways @(Index)for (nBit=0; nBit<=15; nBit=nBit+1)    IndexRev[nBit] = Index[15-nBit];// Input multiplexeralways @(Cntrl or Index or ARCR or ShortImm or IndexRev)begin    IpMux[15:1] = ((ARCR[15:1] & {15{Cntrl[0]}}) |                   ({8'b0,ShortImm[7:1]} & {15{Cntrl[1]}}) |                   (Index[15:1] & {15{(Cntrl[4] & ~Cntrl[3])}}) |                   (IndexRev[15:1] & {15{(Cntrl[4] & Cntrl[3])}}));    IpMux[0] = (ARCR[0] & Cntrl[0]) |               (ShortImm[0] & Cntrl[1]) |               (Index[0] & Cntrl[4] & ~Cntrl[3]) |               (IndexRev[0] & Cntrl[4] & Cntrl[3]) |               ~(Cntrl[0] | Cntrl[1] | Cntrl[4]);end// Adder input inverteralways @(Cntrl or IpMux)    if (Cntrl[2]) AdderIpB = ~IpMux;    else AdderIpB = IpMux;// Bit reverse IpBus for adderalways @(Cntrl or IpBus)for (nBit=0; nBit<=15; nBit=nBit+1)    if (Cntrl[3])        AdderIpA[nBit] = IpBus[15-nBit];    else        AdderIpA[nBit] = IpBus[nBit]; // 16-bit look-ahead adder with carry in and carry outm3s055ct U1 (Cntrl[2], AdderIpA, AdderIpB, AdderOp, C);// Bit reverse output from the adderalways @(Cntrl or AdderOp or IpBus or CBSR1 or CBSR2 or LdCB1 or LdCB2)if (~Cntrl[5]) OpBus = IpBus;else if (LdCB1) OpBus = CBSR1;else if (LdCB2) OpBus = CBSR2;else     for (nBit=0; nBit<=15; nBit=nBit+1)        if (Cntrl[3]) OpBus[nBit] = AdderOp[15-nBit];        else OpBus[nBit] = AdderOp[nBit];// Zero detectalways @(AdderOp)    if (!AdderOp) Z = 1;    else Z = 0;endmodule