//*******************************************************************       ////IMPORTANT NOTICE                                                          ////================                                                          ////Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  ////This file and associated deliverables are the trade secrets,              ////confidential information and copyrighted works of Mentor Graphics         ////Corporation and its licensors and are subject to your license agreement   ////with Mentor Graphics Corporation.                                         ////                                                                          ////These deliverables may be used for the purpose of making silicon for one  ////IC design only.  No further use of these deliverables for the purpose of  ////making silicon from an IC design is permitted without the payment of an   ////additional license fee.  See your license agreement with Mentor Graphics  ////for further details.  If you have further questions please contact        ////Mentor Graphics Customer Support.                                         ////                                                                          ////This Mentor Graphics core (m320c50eng v1999.010) was extracted on         ////workstation hostid 800059c1 Inventra                                      //// DMA Controller// Copyright Mentor Graphics Corporation and Licensors 1998.// V1.007// Revision history// V1.007 - 19 November 1996//          Separate RD, WR signals for each block.//          DataWrite sampling delayed.// m3s019ct// M320C50 Single-port RAM DMA Controller.// External DMA mode enabled by DMAMode signal.// In DMA mode://     SAWA, SARA are connected to AI//     SD is connected to OD.//     DI is driven onto DataWrite.//     SPND forced to 0.//     NSCE derived from decode of AI.//     SRNW is connected to RNWI.//     NSOE, NSWE derived from RNWI and NSTRBI.//// When not in DMA mode OD is generated by sampling DataWrite on the negative edge of Clock.`include "m320c50.inc"module m3s019ct (Clock, DMAMode, ODRegEnab, RNWI, NSTRBI, AI, DI,//*******************************************************************       ////IMPORTANT NOTICE                                                          ////================                                                          ////Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  ////This file and associated deliverables are the trade secrets,              ////confidential information and copyrighted works of Mentor Graphics         ////Corporation and its licensors and are subject to your license agreement   ////with Mentor Graphics Corporation.                                         ////                                                                          ////These deliverables may be used for the purpose of making silicon for one  ////IC design only.  No further use of these deliverables for the purpose of  ////making silicon from an IC design is permitted without the payment of an   ////additional license fee.  See your license agreement with Mentor Graphics  ////for further details.  If you have further questions please contact        ////Mentor Graphics Customer Support.                                         ////                                                                          ////This Mentor Graphics core (m320c50eng v1999.010) was extracted on         ////workstation hostid 800059c1 Inventra                                      //    SD, iSAWA, iSARA, iNSCE, iSPND, iSRNW, iNSWE, iNSOE, iNDEN,    DataWrite, IOD, OD, SAWA, SARA, NSCE, SPND, SRNW, NSWE, NSOE, NDEN);    input         Clock, DMAMode, ODRegEnab, RNWI, NSTRBI;    input         iNDEN;    input  [15:0] DI, SD;    input  [`C_NOSB-1:0] iNSCE, iNSWE, iNSOE, iSPND, iSRNW;    input  [14:0] AI, iSAWA, iSARA;    input  [15:0] DataWrite;    output        NDEN;    output [14:0] SAWA, SARA;    output [15:0] OD, IOD;    output [`C_NOSB-1:0] NSCE, NSWE, NSOE, SPND, SRNW;    reg               NDEN;    reg [14:0]        SAWA, SARA;    reg [15:0]        OD, IOD, DPOD;    reg [`C_NOSB-1:0] WrDMA, RdDMA, WrI, RdI, DMADecode;    reg [`C_NOSB-1:0] NSCE, SPND, SRNW;    reg [15:0]        IntDataWrite, ExtDataWrite;    reg  [3:0]        BlockAddr;    wire [`C_NOSB-1:0] NSWE, NSOE;    integer n;// Decode DMA addressalways @(AI)begin    case (`C_SBS)        0: BlockAddr = AI[13:10];        1: BlockAddr = AI[13:10];        2: BlockAddr = AI[14:11];        3: BlockAddr = {1'b0,AI[14:12]};        4: BlockAddr = {2'b0,AI[14:13]};        5: BlockAddr = {3'b0,AI[14]};        default: BlockAddr = 4'b0;    endcase    for (n=0;n<`C_NOSB;n=n+1)        if (BlockAddr == n) DMADecode[n] = 1;        else DMADecode[n] = 0;end// DMA read/write strobesalways @(RNWI or NSTRBI or DMAMode or DMADecode)    for (n=0;n<`C_NOSB;n=n+1)    begin        WrDMA[n] = (~NSTRBI & ~RNWI) & DMAMode & DMADecode[n];        RdDMA[n] = (~NSTRBI & RNWI) & DMAMode & DMADecode[n];    end// Single-port RAM address bussesalways @(DMAMode or AI or iSAWA or iSARA)    if (DMAMode)    begin        SAWA = AI;        SARA = AI;    end    else    begin        SAWA = iSAWA;        SARA = iSARA;    end// Internal data write busalways @(posedge Clock)    IntDataWrite <= DataWrite;always @(DMAMode or IntDataWrite or DI)    if (DMAMode) IOD = DI;    else IOD = IntDataWrite;// External data write busalways @(posedge Clock)    if (ODRegEnab)        ExtDataWrite <= DataWrite;always @(DMAMode or ExtDataWrite or SD)    if (DMAMode) OD = SD;    else OD = ExtDataWrite;// Single-port block enablesalways @(DMAMode or iNSCE or DMADecode)    if (DMAMode) NSCE = ~DMADecode;    else NSCE = iNSCE;// Single-port prog/data bus selectsalways @(DMAMode or iSPND)    if (DMAMode) SPND = 0;    else SPND = iSPND;// Single-port read/write bus selectsalways @(DMAMode or iSRNW or RNWI)    if (DMAMode)    begin        if (RNWI) SRNW = {`C_NOSB{1'b1}};        else SRNW = 0;    end    else SRNW = iSRNW;// Single-port read/write stobesalways @(DMAMode or iNSOE or iNSWE)begin    WrI = ~{`C_NOSB{DMAMode}} & ~iNSWE;    RdI = ~{`C_NOSB{DMAMode}} & ~iNSOE;endm3s087ct U1 (WrI, WrDMA, RdI, RdDMA, NSWE, NSOE);// Output data enablealways @(DMAMode or NSTRBI or RNWI or iNDEN)    NDEN = ~((~NSTRBI & RNWI) & DMAMode) & (iNDEN | DMAMode);endmodule