//*******************************************************************       ////IMPORTANT NOTICE                                                          ////================                                                          ////Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  ////This file and associated deliverables are the trade secrets,              ////confidential information and copyrighted works of Mentor Graphics         ////Corporation and its licensors and are subject to your license agreement   ////with Mentor Graphics Corporation.                                         ////                                                                          ////These deliverables may be used for the purpose of making silicon for one  ////IC design only.  No further use of these deliverables for the purpose of  ////making silicon from an IC design is permitted without the payment of an   ////additional license fee.  See your license agreement with Mentor Graphics  ////for further details.  If you have further questions please contact        ////Mentor Graphics Customer Support.                                         ////                                                                          ////This Mentor Graphics core (m320c50eng v1999.010) was extracted on         ////workstation hostid 800059c1 Inventra                                      //// Serial Port Transmitter// Copyright Mentor Graphics Corporation and Licensors 1998.// V1.007// Revision history//     V1.007 - 10 July 1997//              LastBit condition removed from clearing of xRegNotEmpty flag// m3s026ct// M320C50 Serial port transmitter.// DX is the output data, NDXE the enable xmit data line (low true)// FSXI and FSXO are the Frame Synchronisation signals for transmit// operation (input and output respectively)// FO, FSM, TXM are control bits from the SPC register// TxRegNotEmpty is the transmit underflow flag for the control register// TxRdy is the transmit ready flag// XRST is the transmit reset line (low true)// XINT is the transmit interrupt// Note for higher levels, the XINT interrupt must be tested for as a// transition from 0 to 1, not as a level.// Also: the TxReset input must be driven at least 2 TxClock periods before the// clocks stop// Latencies: 	DXR write to DX out//               min 2 TxClock//               max 3 TxClock// State machine definitions`define C_DXR_EMPTY_XSR_EMPTY 0`define C_DXR_FULL_XSR_EMPTY  1`define C_DXR_EMPTY_XSR_FULL  2`define C_DXR_FULL_XSR_FULL   3module m3s026ct (Clock, TxClock, NTxClock, TxReset, MMRWriteData, WriteDXR,//*******************************************************************       ////IMPORTANT NOTICE                                                          ////================                                                          ////Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  ////This file and associated deliverables are the trade secrets,              ////confidential information and copyrighted works of Mentor Graphics         ////Corporation and its licensors and are subject to your license agreement   ////with Mentor Graphics Corporation.                                         ////                                                                          ////These deliverables may be used for the purpose of making silicon for one  ////IC design only.  No further use of these deliverables for the purpose of  ////making silicon from an IC design is permitted without the payment of an   ////additional license fee.  See your license agreement with Mentor Graphics  ////for further details.  If you have further questions please contact        ////Mentor Graphics Customer Support.                                         ////                                                                          ////This Mentor Graphics core (m320c50eng v1999.010) was extracted on         ////workstation hostid 800059c1 Inventra                                      //      FO, FSM, TXM, FSXI,      FSXO, DX, NDXE, TxRegNotEmpty, TxRdy, NextDXR, XINT);  input  [15:0] MMRWriteData;  input         Clock, TxClock, NTxClock, TxReset, WriteDXR;  input         FO, FSM, TXM, FSXI;  output [15:0] NextDXR;  output        FSXO, DX, NDXE, TxRegNotEmpty, XINT, TxRdy;    reg [15:0] DXR, NextDXR, XSR;  reg        TxRegNotEmpty;  reg  [3:0] TxCount;  reg        NDXE, LocalFSX, InternalFSX, SampleFSX;  reg        XINT, TxRdy, TxRdyReg, ClrTxRdy, DX, LdXSRInt;  reg        WrDXRSync, WrDXRSig;  reg  [1:0] TxState;  reg        FSXO, LastBit, L_Bit, TxRdyIp, Shift_XSR;//// DXR register//always @(MMRWriteData or WriteDXR or DXR)begin    if (WriteDXR) NextDXR = MMRWriteData;    else NextDXR = DXR;endalways @(posedge Clock)begin    WrDXRSig <= WriteDXR | (WrDXRSig & ~WrDXRSync & TxReset);    DXR <= NextDXR;end//// synchronise WriteDXR -> WrDXRSync, 1 TxClock period.// assumes WriteDXR is less than 1 TxClock period long//always @(posedge TxClock or negedge TxReset)begin  if (~TxReset) WrDXRSync <= 1'b0;  else  WrDXRSync <= WrDXRSig;end//// transmit control state machine//always @(posedge NTxClock or negedge TxReset) // negedge because TxRdy changes on thisbegin    if (~TxReset) TxState <= `C_DXR_EMPTY_XSR_EMPTY; // reset state    else    case (TxState)        `C_DXR_EMPTY_XSR_EMPTY: // can only go one place from here            if (WrDXRSync) TxState <= `C_DXR_FULL_XSR_EMPTY; // write fills DXR        `C_DXR_FULL_XSR_EMPTY: TxState <= `C_DXR_EMPTY_XSR_FULL; // this state always only 1 TxClock        `C_DXR_EMPTY_XSR_FULL: // either get another write or empty            if (WrDXRSync && !L_Bit) TxState <= `C_DXR_FULL_XSR_FULL;	    else if (WrDXRSync && L_Bit) TxState <= `C_DXR_EMPTY_XSR_FULL;	    else if (L_Bit) TxState <= `C_DXR_EMPTY_XSR_EMPTY;        `C_DXR_FULL_XSR_FULL: // can only go to one place from here            if (L_Bit) TxState <= `C_DXR_EMPTY_XSR_FULL;        default: // there isn't one but for safety            TxState <= TxState;    endcaseend//// generate LastBit signal//always @(TxCount or NDXE)begin    LastBit = (TxCount == 14);    L_Bit = ((TxCount == 15) && ~NDXE);end//// generate shift control//always @(SampleFSX or NDXE or L_Bit)begin    Shift_XSR = (SampleFSX | (~NDXE & ~L_Bit));end//// TxRegNotEmpty flag synchronised//always @(posedge TxClock)begin    if (~TxReset) TxRegNotEmpty <= 0;        else if (TxState == `C_DXR_FULL_XSR_EMPTY) TxRegNotEmpty <= 1;    else if ((TxState == `C_DXR_EMPTY_XSR_EMPTY) && !WrDXRSync)        TxRegNotEmpty <= 0;end//// Transmit counter - counts 0,1,2,3,4,5,14,15 if FO == 1, 0 to 15 if FO == 0//always @(posedge TxClock or negedge TxReset)begin    if (~TxReset) begin       // asynchronous set        TxCount <= 4'b1111 ;        NDXE <= 1 ;    end    else if (SampleFSX) begin // synchronous reset of counter        TxCount <= 4'b0 ;        NDXE <= 0 ;    end    else if (FO == 1 && TxCount == 5) // FO controls 8/16 bit operation	TxCount <= 4'b1110;    else if (TxCount < 15) TxCount <= TxCount + 1;    else NDXE <= 1 ;         // turn off transmit if last bit already goneend//// Frame Sync control// sample LocalFSX//always @(posedge NTxClock or negedge TxReset)begin    if (~TxReset) SampleFSX <= 0;    else SampleFSX <= LocalFSX;end//// internal FSX pulses//always @(posedge TxClock or negedge TxReset)begin    if (~TxReset) InternalFSX <= 0;    else if ((TxState == `C_DXR_FULL_XSR_EMPTY) && TXM && (TxCount == 15))        InternalFSX <= 1;    else if ((TxState == `C_DXR_FULL_XSR_FULL) && (TXM | ~FSM) && (TxCount == 14))        InternalFSX <= 1;    else InternalFSX <= 0;end//    // only output FSX pulses for first frame after idle if FSM is 0//always @(InternalFSX or NDXE or FSM)begin    FSXO = (InternalFSX & (NDXE | FSM)); end//// combine internal and external FSX signals into signal LocalFSX//always @(TXM or FSM or InternalFSX or FSXI or TxRegNotEmpty or NDXE)begin    if (TXM)       // source FSX pulses internal or external        LocalFSX = InternalFSX ;    else if (FSM)  // Frame Sync mode always allows FSX pulses        LocalFSX = FSXI ;    else if (~NDXE | TxRegNotEmpty) // allow aborts but no retransmit of old data        LocalFSX = FSXI | InternalFSX;    else        LocalFSX = 0; // disable if idle in continuous mode    end//// XSR = transmit shift register//always @(posedge TxClock)begin    case (TxState) // NOTE: all states covered    `C_DXR_EMPTY_XSR_FULL: if (Shift_XSR) XSR <= {XSR[14:0],1'b0};  // shift    `C_DXR_FULL_XSR_FULL: if (LastBit) XSR <= DXR;                          else if (Shift_XSR) XSR <= {XSR[14:0],1'b0};    default: XSR <= DXR ; // default feedback    endcaseend//// output data synchronised to other edge//always @(posedge TxClock)begin    if (FO) DX <= XSR[7];    else DX <= XSR[15];end//// generate TxRdyIp signal on load of XSR//always @(TxState or LastBit or TxReset)begin    TxRdyIp = ((TxState == `C_DXR_FULL_XSR_EMPTY)       || ((TxState == `C_DXR_FULL_XSR_FULL) && LastBit)       || !TxReset);end//// generate TxRdy clear signal from WriteDXR//always @(posedge Clock or negedge TxReset)begin    if (!TxReset) ClrTxRdy <= 0;    else ClrTxRdy <= (WriteDXR | (ClrTxRdy & TxRdyReg));end//// generate TxRdy signal//always @(posedge NTxClock or negedge TxReset)begin    if (!TxReset) TxRdyReg <= 1;    else TxRdyReg <= (TxRdyIp | (TxRdyReg & ~ClrTxRdy));endalways @(TxRdyReg or ClrTxRdy or WriteDXR)begin    TxRdy = TxRdyReg & ~(ClrTxRdy | WriteDXR);end//// generate transmit interrupts on TxRdy transition//always @(posedge TxClock)begin    LdXSRInt <= ((TxState == `C_DXR_FULL_XSR_EMPTY)       || ((TxState == `C_DXR_FULL_XSR_FULL) && LastBit));endalways @(posedge Clock or negedge TxReset)begin   if (~TxReset) XINT <= 0;   else XINT <= LdXSRInt;endendmodule