// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files any of the foregoing 
// (including device programming or simulation files), and any 
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// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
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// applicable agreement for further details.

// *****************************************************************************
// This file contains a Verilog test bench template that is freely editable to  
// suit user's needs .Comments are provided in each section to help the user    
// fill out necessary details.                                                  
// *****************************************************************************
// Generated on "01/12/2006 11:26:30"
                                                                                
// Verilog Test Bench template for design : sys_TMS320C50
// 
// Simulation tool : ModelSim (Verilog)
// 

`timescale 1 ns/ 1 ps
module sys_TMS320C50_vlg_tst();
// constants                                           
// general purpose registers                           
reg eachvec;                                           
// test vector input registers                         
reg t__reg__NRS;
reg t__reg__NINT1;
reg t__reg__NINT2;
reg t__reg__NMI;
reg t__reg__CLK;
// wires                                               
wire t__wire__NRS;
wire t__wire__NINT1;
wire t__wire__NINT2;
wire t__wire__NMI;
wire t__reg__NDS_O;
wire t__reg__NPS_O;
wire t__reg__NIS_O;
wire t__reg__NRD_O;
wire t__reg__NWR_O;
wire t__reg__NHOLDA;
wire t__reg__NIAQ;
wire t__reg__XF;
wire t__reg__NIACK;
wire t__reg__CLKOUT1;
wire t__reg__X1;
wire t__reg__TOUT;
wire t__reg__DX_O;
wire t__reg__TDX_O;
wire t__reg__TDO;
wire [15:0] t__wire__A_O;
wire [15:0] t__wire__D_O;
wire t__wire__RNW;
wire t__wire__NSTB;
wire t__wire__NBR_O;
wire t__wire__CLKX;
wire t__wire__TCLKX;
wire t__wire__TFSR;
wire t__wire__FSX;
wire t__wire__TFSX;
wire t__wire__CLK;

// assign statements (if any)                          
assign {t__wire__NRS,t__wire__NINT1,t__wire__NINT2,t__wire__NMI,t__wire__CLK} = {t__reg__NRS,t__reg__NINT1,t__reg__NINT2,t__reg__NMI,t__reg__CLK};
sys_TMS320C50 i1 (
// port map - connection between master ports and signals/registers   
.NRS(t__wire__NRS),.NINT1(t__wire__NINT1),.NINT2(t__wire__NINT2),.NMI(t__wire__NMI),.NDS_O(t__wire__NDS_O),.NPS_O(t__wire__NPS_O),.NIS_O(t__wire__NIS_O),.NRD_O(t__wire__NRD_O),.NWR_O(t__wire__NWR_O),.NHOLDA(t__wire__NHOLDA),.NIAQ(t__wire__NIAQ),.XF(t__wire__XF),.NIACK(t__wire__NIACK),.CLKOUT1(t__wire__CLKOUT1),.X1(t__wire__X1),.TOUT(t__wire__TOUT),.DX_O(t__wire__DX_O),.TDX_O(t__wire__TDX_O),.TDO(t__wire__TDO),.A_O(t__wire__A_O),.D_O(t__wire__D_O),.RNW(t__wire__RNW),.NSTB(t__wire__NSTB),.NBR_O(t__wire__NBR_O),.CLKX(t__wire__CLKX),.TCLKX(t__wire__TCLKX),.TFSR(t__wire__TFSR),.FSX(t__wire__FSX),.TFSX(t__wire__TFSX),.CLK(t__wire__CLK));
initial                                                
begin                                                  
// code that executes only once                        
// insert code here --> begin                          
 t__reg__CLK=0; //Clock input, twice the instruction cycle rate.
 t__reg__NRS=0; //Reset, active low.
 t__reg__NINT1=1;
 t__reg__NINT2=1;
 t__reg__NMI=1;
// --> end                                             
$display("Running testbench");                       
end                                                    
always                                                 
// optional sensitivity list                           
// @(event1 or event2 or .... eventn)                  
begin                                                  
// code executes for every event on sensitivity list   
// insert code here --> begin                          
 #5 t__reg__CLK=~t__reg__CLK;                                                                                                             
//@eachvec;                                              
// --> end                                             
end
 
initial                                                
begin                                                  
// code that executes only once                        
// insert code here --> begin                          
 #500 t__reg__NRS=0;
      
 #4000 t__reg__NRS=1;
 #1000 t__reg__NRS=1;
 #500000000 t__reg__NRS=1;                                     
// --> end                                             
$display("Running testbench");                       
end                                                    

endmodule