module RAM04_Control (NSCE,SRNW,SAWA,NSWE,NSOE,SPND,SAPA,SARA,IOD,q04,address04,data04,PD04,SD04,wren04);

input  [5-1:0] NSCE,SRNW,NSWE,NSOE,SPND;
input  [14:0] SAWA,SAPA,SARA;
input  [15:0] IOD,q04;
output  [10:0] address04;
output  [15:0] data04,PD04,SD04;
output  wren04;

reg  [15:0] iPSD,iSD;
reg  [15:0] idata04;
reg  iwren04;
reg  [10:0] iaddress04;
reg  [15:0] PD04,SD04;
reg  [15:0] data04;
reg  wren04;
reg  [10:0] address04;

always @(SARA or SAWA or SAPA or SPND or SRNW or
         IOD or SPND or NSWE or NSOE or q04)
 begin
  if (!NSWE[4] & !SRNW[4])
   begin 
    iaddress04 = SAWA[10:0];
    idata04 = IOD;
    iwren04 = ~NSWE[4];
   end
  else
   begin 
    iaddress04 = 11'bz;
    idata04 = 16'bz;
    iwren04 = 1'bz;
   end

  if (SPND[4])
   begin
    iPSD = q04;
    iSD = q04;
    if (!NSOE[4] & SRNW[4])
     begin
      iaddress04 = SAPA[10:0];      
     end
    else
     begin
      iaddress04 = 11'bz; 
     end
   end
  else
   begin
    iPSD = 16'bz;
    iSD = 16'bz;
    if (!NSOE[4] & SRNW[4]) 
     begin
      iaddress04 = SARA[10:0];
     end
    else
     begin
      iaddress04 = 11'bz; 
     end
   end
 end
   

always @(NSCE or iPSD or iSD or idata04 or iwren04 or iaddress04)
 begin
  if (!NSCE[4])
   begin
    PD04 = iPSD;
    SD04 = iSD;
    data04 = idata04;
    wren04 = iwren04;
    address04 = iaddress04;
   end
  else
   begin
    PD04 = 16'bz;
    SD04 = 16'bz;
    data04 = 16'bz;
    wren04 = 1'bz;
    address04 = 11'bz;
   end
 end
   
endmodule