//*******************************************************************       ////IMPORTANT NOTICE                                                          ////================                                                          ////Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  ////This file and associated deliverables are the trade secrets,              ////confidential information and copyrighted works of Mentor Graphics         ////Corporation and its licensors and are subject to your license agreement   ////with Mentor Graphics Corporation.                                         ////                                                                          ////These deliverables may be used for the purpose of making silicon for one  ////IC design only.  No further use of these deliverables for the purpose of  ////making silicon from an IC design is permitted without the payment of an   ////additional license fee.  See your license agreement with Mentor Graphics  ////for further details.  If you have further questions please contact        ////Mentor Graphics Customer Support.                                         ////                                                                          ////This Mentor Graphics core (m320c50eng v1999.010) was extracted on         ////workstation hostid 800059c1 Inventra                                      //// Data Address Generator// Copyright Mentor Graphics Corporation and Licensors 1998.// V1.109// Revision history// V1.109 - 2 December 1996//          DFCAuxReg input added.// V1.108 - 20 November 1996//          Inputs for putting write data on DataRead.//          Number of tri-state drivers on DataRead reduced.// m3s005ct// M320C50 Data address generator and auxillary registers.// Provides the 16-bit data write address and data read address.// With direct addressing the upper 9-bits of the address are the data page// and the lower 7 bits are defined in the instruction.// With indirect addressing the address comes from the auxillary registers.// The auxillary registers are updated at the end of the decode cycle, so the// previous 2 auxillary register values are stored for use in the read and// write cycles.// The memory block being accessed is decoded and one of the request lines// will go high.// A look-ahead carry incrementer is used to increment the WriteAddr for// internal memory data moves.//// DACntrl usage://     0 : Read request//     1 : Read indirect (1 = indirect, 0 = direct)//     2 : Read immediate (1 = immediate)//     3 : Read suppress Data Page//     4 : Read from I/O address//     5 : Write request//     6 : Write indirect (1 = indirect, 0 = direct)//     7 : Write immediate (1 = immediate)//     8 : Write suppress Data Page//     9 : Write to I/O address//    10 : Write DMOV//    11 : Load ST0//    12 : Load ST1//    13 : Read ST0//    14 : Read ST1//    15 : LAR from data bus//    16 : LAR from prog bus//    17 : Modify AR//    18 : Load ARP//    19 : Aux Reg compare with ARCR//    20 : Short Immediate operand// 23:21 : ARAU control//    24 : Store Aux reg// 28:26 : Next ARP / CM bits// 31:29 : Aux reg store address//    32 : Stall Aux register updates//    33 : I/O Access//// LdCntrl usage://     1 : Load DP from data bus//     2 : Load DP from program bus//// Memory block decodes://    DpReq : Dual-port blocks 2-0//    SpReq : Single-port//    ExReq : External`include "m320c50.inc"`define C_B0Start 16'h0100    // Start of dual-port RAM block 0`define C_B0Size 16'h0200     // Size dual-port RAM block 0`define C_B1Start 16'h0300    // Start of dual-port RAM block 1`define C_B1Size 16'h0200     // Size dual-port RAM block 1`define C_B2Start 16'h0060    // Start of dual-port RAM block 2`define C_B2Size 16'h0020     // Size dual-port RAM block 2`define C_ExStart 16'h0800    // Start of external/single-port data memory`define C_MMPStart 16'h0050   // Start of memory mapped IO ports`define C_MMPEnd 16'h0060     // End of memory mapped IO portsmodule m3s005ct (DataBus, ProgBus, RdAddr, WrAddr, ShortImm, LdPortAddr,//*******************************************************************       ////IMPORTANT NOTICE                                                          ////================                                                          ////Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  ////This file and associated deliverables are the trade secrets,              ////confidential information and copyrighted works of Mentor Graphics         ////Corporation and its licensors and are subject to your license agreement   ////with Mentor Graphics Corporation.                                         ////                                                                          ////These deliverables may be used for the purpose of making silicon for one  ////IC design only.  No further use of these deliverables for the purpose of  ////making silicon from an IC design is permitted without the payment of an   ////additional license fee.  See your license agreement with Mentor Graphics  ////for further details.  If you have further questions please contact        ////Mentor Graphics Customer Support.                                         ////                                                                          ////This Mentor Graphics core (m320c50eng v1999.010) was extracted on         ////workstation hostid 800059c1 Inventra                                      //    B0D, B1D, B2D, SD, DI, DACntrl, LdCntrl, AuxRegCntrl, NextARAddr,    Clock, Reset, AdvCycle, MemCycle, MemCycle1, OVLY, CNF,    ContextSave, ContextRestore, iMMR, NDX, DMAMode, DFCAuxStall,    MMWrRq, MMRdRq, PrWrRdy, SpWrRdy, ExWrRdy, SpRdWrDet, DpRdWrDet,    DpWrRq, SpWrRq, ExWrRq, IOWrRq, DpRdRq, SpRdRq, ExRdRq, IORdRq,    WriteAddr, ReadAddr, WriteReady, ARZ, ARTC, DataWrite, DataRead);    input [15:0] DataBus, ProgBus, B0D, B1D, B2D, SD, DI;    input  [6:0] RdAddr, WrAddr;    input [33:0] DACntrl;    input  [1:0] LdCntrl;    input [15:0] AuxRegCntrl;    input  [2:0] NextARAddr;    input  [7:0] ShortImm;    input        Clock, Reset, AdvCycle, MemCycle, MemCycle1, LdPortAddr, iMMR, NDX;    input        OVLY, CNF, ContextSave, ContextRestore, DMAMode, DFCAuxStall;    input        PrWrRdy, SpWrRdy, ExWrRdy, SpRdWrDet, DpRdWrDet;    inout  [15:0] DataWrite;    output [15:0] WriteAddr, ReadAddr, DataRead;    output        WriteReady, ARZ, ARTC;    output  [2:0] DpRdRq, DpWrRq;    output        SpRdRq, ExRdRq, SpWrRq, ExWrRq, MMRdRq, MMWrRq, IORdRq, IOWrRq;    wire [15:0] ReadAddr, WriteAddr, RdPortAddr;    wire [8:0] DataPage;    wire [2:0] DpRdRq, DpWrRq;    wire       SpWrRq, SpRdRq, ExWrRq, ExRdRq;    wire       MMWrRq, MMRdRq, IOWrRq, IORdRq;    reg [15:0] NextReadAddr, DataReadMux;    reg  [2:0] ARAddr;    reg [15:0] AuxIpBus, WriteAddrN, WriteDMA, ReadDMA;    reg [15:0] NextPortAddr, NextRdPortAddr, WrPortAddr, WrImm;    reg  [8:0] NextDataPage, DataPage_C;    reg        WriteReady;    reg        NextSpWrRq, NextSpRdRq;    reg        NextExWrRq, NextExRdRq;    reg        NextMMWrRq, NextMMRdRq;    reg        NextIOWrRq, NextIORdRq;    reg  [2:0] NextDpRdRq, NextDpWrRq;    wire [15:0] NextWriteAddr, WriteAuxReg, ReadAuxReg, PortAddrInc;    tri  [15:0] DataWrite;    wire        ARZ, ARTC;// Data pagealways @(LdCntrl or DACntrl or ContextRestore or DataBus or ProgBus      or DataPage_C or DataPage)    if (LdCntrl[0] | DACntrl[11]) NextDataPage = DataBus[8:0];    else if (LdCntrl[1]) NextDataPage = ProgBus[8:0];    else if (ContextRestore) NextDataPage = DataPage_C;    else NextDataPage = DataPage;always @(posedge Clock)begin    if (ContextSave) DataPage_C <= NextDataPage;end// Auxillary block input multiplexeralways @(DACntrl or ProgBus or DataBus)    if (DACntrl[16])        AuxIpBus = ProgBus;    else        AuxIpBus = DataBus;// Auxillary registersm3s006ct U1 (AuxIpBus, WriteAddr[2:0], ReadAddr[2:0], ShortImm,    ARAddr, Clock, Reset, AdvCycle, MemCycle, MemCycle1, ContextSave, ContextRestore,    AuxRegCntrl, DACntrl[32:11], iMMR, NDX, DMAMode, DFCAuxStall,    ReadAuxReg, WriteAuxReg, DataWrite, DataRead, ARZ, ARTC);// Immediate write address and ARAddralways @(posedge Clock)    if (MemCycle)    begin        WrImm <= ProgBus;        ARAddr <= NextARAddr;    end// Port address load multiplexeralways @(LdPortAddr or RdPortAddr or ProgBus)    if (LdPortAddr) NextPortAddr = ProgBus;    else NextPortAddr = RdPortAddr;// Port address incrementerm3s080ct U4 (NextPortAddr, PortAddrInc);// Port address read register muxalways @(DACntrl or LdPortAddr or PortAddrInc or RdPortAddr)    if (DACntrl[9] | (DACntrl[4] & DACntrl[0]) | LdPortAddr)        NextRdPortAddr = PortAddrInc;    else        NextRdPortAddr = RdPortAddr;// Write Port address registeralways @(posedge Clock)if (MemCycle)    WrPortAddr <= RdPortAddr;// Write address multiplexeralways @(DACntrl or DataPage or WriteAuxReg or WrAddr or ProgBus or WrPortAddr or WrImm)begin    if (DACntrl[6]) WriteDMA = WriteAuxReg;    else WriteDMA = {DataPage,WrAddr};    case (DACntrl[9:7])        0: WriteAddrN = WriteDMA;        1: WriteAddrN = WrImm;        2: WriteAddrN = {9'b0,WriteDMA[6:0]};        3: WriteAddrN = WrImm;        default: WriteAddrN = WrPortAddr;    endcaseend// DMOV incrementerm3s040ct U2 (WriteAddrN, DACntrl[10], NextWriteAddr);// Read address multiplexeralways @(DACntrl or NextDataPage or ReadAuxReg or RdAddr or ProgBus or RdPortAddr)begin    if (DACntrl[1]) ReadDMA = ReadAuxReg;    else ReadDMA = {NextDataPage,RdAddr};    case (DACntrl[4:2])        0: NextReadAddr = ReadDMA;        1: NextReadAddr = ProgBus;        2: NextReadAddr = {9'b0,ReadDMA[6:0]};        3: NextReadAddr = ProgBus;        default: NextReadAddr = RdPortAddr;    endcaseend// Registersm3s049ct U3 (Clock, Reset, MemCycle,  NextReadAddr, NextWriteAddr, NextDataPage, NextRdPortAddr,  NextIORdRq, NextDpRdRq, NextSpRdRq, NextExRdRq, NextMMRdRq,  NextIOWrRq, NextDpWrRq, NextSpWrRq, NextExWrRq, NextMMWrRq,  ReadAddr, WriteAddr, DataPage, RdPortAddr,  IORdRq, DpRdRq, SpRdRq, ExRdRq, MMRdRq,  IOWrRq, DpWrRq, SpWrRq, ExWrRq, MMWrRq);// Read memory device decoderalways @(DACntrl or NextReadAddr or OVLY or CNF)begin    if (DACntrl[33] & DACntrl[2] & DACntrl[0])    begin        NextIORdRq = 1;        NextDpRdRq = 0;        NextSpRdRq = 0;        NextExRdRq = 0;        NextMMRdRq = 0;    end    else    begin    if ((NextReadAddr >= `C_B0Start) && (NextReadAddr < `C_B0Start + `C_B0Size) & ~CNF &       DACntrl[0])        NextDpRdRq[0] = 1;    else        NextDpRdRq[0] = 0;    if ((NextReadAddr >= `C_B1Start) && (NextReadAddr < `C_B1Start + `C_B1Size) &       DACntrl[0])        NextDpRdRq[1] = 1;    else        NextDpRdRq[1] = 0;    if ((NextReadAddr >= `C_B2Start) && (NextReadAddr < `C_B2Start + `C_B2Size) &       DACntrl[0])        NextDpRdRq[2] = 1;    else        NextDpRdRq[2] = 0;    if ((NextReadAddr >= `C_ExStart) && (NextReadAddr < `C_ExStart + {`C_SR,10'b0}) & OVLY &       DACntrl[0])        NextSpRdRq = 1;    else        NextSpRdRq = 0;    if ((NextReadAddr >= `C_ExStart) & ~NextSpRdRq & DACntrl[0])        NextExRdRq = 1;    else        NextExRdRq = 0;    if ((NextReadAddr < `C_B2Start) & DACntrl[0])    begin        if ((NextReadAddr >= `C_MMPStart) & (NextReadAddr < `C_MMPEnd))            NextIORdRq = 1;        else            NextIORdRq = 0;        NextMMRdRq = ~NextIORdRq;    end    else    begin        NextIORdRq = 0;        NextMMRdRq = 0;    end    endend// Write memory device decoderalways @(DACntrl or NextWriteAddr or OVLY or CNF)begin    if (DACntrl[33] & DACntrl[7] & DACntrl[5])    begin        NextIOWrRq = 1;        NextDpWrRq = 0;        NextSpWrRq = 0;        NextExWrRq = 0;        NextMMWrRq = 0;    end    else    begin    if ((NextWriteAddr >= `C_B0Start) && (NextWriteAddr < `C_B0Start + `C_B0Size) & ~CNF &       DACntrl[5])        NextDpWrRq[0] = 1;    else        NextDpWrRq[0] = 0;    if ((NextWriteAddr >= `C_B1Start) && (NextWriteAddr < `C_B1Start + `C_B1Size) &       DACntrl[5])        NextDpWrRq[1] = 1;    else        NextDpWrRq[1] = 0;    if ((NextWriteAddr >= `C_B2Start) && (NextWriteAddr < `C_B2Start + `C_B2Size) &       DACntrl[5])        NextDpWrRq[2] = 1;    else        NextDpWrRq[2] = 0;    if ((NextWriteAddr >= `C_ExStart) && (NextWriteAddr < `C_ExStart + {`C_SR,10'b0}) & OVLY &       DACntrl[5])        NextSpWrRq = 1;    else        NextSpWrRq = 0;    if ((NextWriteAddr >= `C_ExStart) & ~NextSpWrRq & DACntrl[5] & ~DACntrl[10])        NextExWrRq = 1;    else        NextExWrRq = 0;    if ((NextWriteAddr < `C_B2Start) & DACntrl[5])    begin        if ((NextWriteAddr >= `C_MMPStart) & (NextWriteAddr < `C_MMPEnd))            NextIOWrRq = 1;        else            NextIOWrRq = 0;        NextMMWrRq = ~NextIOWrRq;    end    else    begin        NextIOWrRq = 0;        NextMMWrRq = 0;    end    endend// Write ready signalsalways @(PrWrRdy or SpWrRdy or ExWrRdy)    WriteReady = PrWrRdy & SpWrRdy & ExWrRdy;// ST0 readassign DataWrite[8:0] = (DACntrl[13] & ~DMAMode) ? NextDataPage : 9'bZ;// Data memory read multiplexeralways @(DpRdRq or SpRdRq or SpRdWrDet or DpRdWrDet or ExRdRq or IORdRq or    B0D or B1D or B2D or SD or DI or DataWrite)    if (SpRdWrDet | DpRdWrDet)        DataReadMux = DataWrite;    else        DataReadMux = ({16{DpRdRq[0]}} & B0D) |                      ({16{DpRdRq[1]}} & B1D) |                      ({16{DpRdRq[2]}} & B2D) |                      ({16{SpRdRq}} & SD) |                      ({16{(ExRdRq | IORdRq)}} & DI);assign DataRead = (DpRdRq[0] | DpRdRq[1] | DpRdRq[2] | SpRdRq | ExRdRq | IORdRq) ?    DataReadMux : 16'bZ;endmodule