//*******************************************************************       ////IMPORTANT NOTICE                                                          ////================                                                          ////Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  ////This file and associated deliverables are the trade secrets,              ////confidential information and copyrighted works of Mentor Graphics         ////Corporation and its licensors and are subject to your license agreement   ////with Mentor Graphics Corporation.                                         ////                                                                          ////These deliverables may be used for the purpose of making silicon for one  ////IC design only.  No further use of these deliverables for the purpose of  ////making silicon from an IC design is permitted without the payment of an   ////additional license fee.  See your license agreement with Mentor Graphics  ////for further details.  If you have further questions please contact        ////Mentor Graphics Customer Support.                                         ////                                                                          ////This Mentor Graphics core (m320c50eng v1999.010) was extracted on         ////workstation hostid 800059c1 Inventra                                      //// Interrupt Controller// Copyright Mentor Graphics Corporation and Licensors 1998. // V1.104// Revision history// V1.104 - 22 April 1998//          Resynchronisation flip-flop added before IntProc to reduce//          clock skew sensitivity.// V1.103 - 27 June 1997//          Number of tri-state drivers reduced.// m3s060ct// M320C50 CPU core interrupt controller.// Provides sixteen maskable interrupts and one non-maskable interrupt.//// INPUTS:// Intr    : 16 maskable interrupts (active high)// NMIEdge : Non-maskable interrupt (active high)//// IntrStuff : Indicates that the interrupt instruction has been//             jammed into the instruction pipeline.// IntrEx    : Indicates that it is executing.//// IntRegCntrl://    0 : Write IMR//    1 : Write IFR//    2 : Read IMR//    3 : Read IFR//// OUTPUTS:// IntReq  : Indicates that an interrupt is pending.// IntVect : The interrupt number of the highest priority pending interrupt.//// The interrupt inputs are re-synchronised to the negative edge of the clock// to avoid clock skew problems (they were generated from ClockSys not ClockCPU).module m3s060ct (DataBus, IntRegCntrl, RdST0, LdINTM, INTMVal, iMMR, MemAccEnab,//*******************************************************************       ////IMPORTANT NOTICE                                                          ////================                                                          ////Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  ////This file and associated deliverables are the trade secrets,              ////confidential information and copyrighted works of Mentor Graphics         ////Corporation and its licensors and are subject to your license agreement   ////with Mentor Graphics Corporation.                                         ////                                                                          ////These deliverables may be used for the purpose of making silicon for one  ////IC design only.  No further use of these deliverables for the purpose of  ////making silicon from an IC design is permitted without the payment of an   ////additional license fee.  See your license agreement with Mentor Graphics  ////for further details.  If you have further questions please contact        ////Mentor Graphics Customer Support.                                         ////                                                                          ////This Mentor Graphics core (m320c50eng v1999.010) was extracted on         ////workstation hostid 800059c1 Inventra                                      //    ClockCPU, Clock, Reset, MemCycle, IntrStuff, IntrEx, NMIEdge, Intr, ClrIntm, SetIntm,    NextINTM, IntReq, IntFreeze, Wakeup, DataWrite, DataRead);	  input  [3:0] IntRegCntrl;  input [15:0] Intr;  input        NMIEdge;  input        ClockCPU, Clock, Reset, MemCycle;  input        RdST0, LdINTM, INTMVal, iMMR, MemAccEnab;  input        IntrStuff, IntrEx, ClrIntm, SetIntm;  input  [15:0] DataBus;  inout  [15:0] DataWrite;  output [15:0] DataRead;  output  [4:0] IntFreeze;  output        NextINTM, IntReq, Wakeup;    reg [15:0] IMR, IFR, IntMasked, ClearIFR, NextIMR, NextIFR, IntrSync;  reg [16:0] NIAcks;  reg        INTM, NextINTM, IntReq, IntGen, NMISync;  reg        IntProc, IntWake, Wakeup, WakeupSync, IntWakeSync;  reg        IntAck, NMI, UMInt;  reg  [4:0] IntVect, IntFreeze;  reg        ResetNeg, IntrExSync, IntrStuffSync, IntProcSync;  reg [15:0] DataReadOp;// Reset synchronised to positive edge of clockalways @(posedge Clock)    ResetNeg <= Reset;// Resynchronise interrupt inputsalways @(negedge Clock or posedge ResetNeg)    if (ResetNeg)    begin        IntrSync <= 0;        NMISync <= 0;        IntrExSync <= 0;        IntrStuffSync <= 0;        IntWakeSync <= 0;    end    else    begin        IntrSync <= Intr;        NMISync <= NMIEdge;        IntrExSync <= IntrEx;        IntrStuffSync <= IntrStuff;        IntWakeSync <= IntWake & ~INTM;    end// IMR register ** NOT INITIALISED BY RESET **always @(IntRegCntrl or iMMR or DataBus or DataWrite or IMR)    if (IntRegCntrl[0] & iMMR) NextIMR = DataBus;    else if (IntRegCntrl[0] & ~iMMR) NextIMR = DataWrite;    else NextIMR = IMR;always @(posedge Clock)    if (MemCycle) IMR <= NextIMR;// IFR registeralways @(IntRegCntrl or DataBus or MemCycle or iMMR or DataWrite)    if (IntRegCntrl[1] & iMMR & MemCycle) ClearIFR = DataBus;    else if (IntRegCntrl[1] & ~iMMR & MemCycle) ClearIFR = DataWrite;    else ClearIFR = 16'b0;always @(NIAcks or ClearIFR or IntrSync or IFR)    NextIFR = NIAcks[15:0] & ~ClearIFR & (IntrSync | IFR);always @(posedge Clock or posedge Reset)    if (Reset) IFR <= 0;    else IFR <= NextIFR;// Latch NMIalways @(posedge Clock or posedge Reset)    if (Reset)        NMI <= 0;    else if (NMI)        NMI <= NIAcks[16];    else        NMI <= NMISync;// INTM bitalways @(Reset or LdINTM or SetIntm or ClrIntm  or INTMVal or INTM)    if (Reset)        NextINTM = 1;    else if (LdINTM)        NextINTM = INTMVal;    else if (SetIntm)        NextINTM = 1;    else if (ClrIntm)        NextINTM = 0;    else        NextINTM = INTM;always @(posedge Clock)    if (MemCycle) INTM <= NextINTM;// Mask the interruptsalways @(IFR or IMR)    IntMasked = IFR & IMR;// Generate Idle mode wake-up signalalways @(posedge Clock or posedge Reset)    if (Reset)        UMInt <= 0;    else        UMInt <= (NMI | (IntMasked != 0));always @(negedge Clock or posedge ResetNeg)    if (ResetNeg)        Wakeup <= 0;    else        Wakeup <= (NMI | (IntMasked != 0));// Generate an interruptalways @(NMI or IntMasked or INTM or IntProc or MemAccEnab)    if ((NMI | ((IntMasked != 0) & ~INTM)) & ~IntProc & MemAccEnab)        IntGen = 1;    else        IntGen = 0;// Interrupt requestalways @(negedge Clock or posedge ResetNeg)    if (ResetNeg)        IntReq <= 0;    else if (IntReq)        IntReq <= ~(IntProc | IntrEx | (INTM & ~NMI));    else        IntReq <= IntGen;// Priority encoderalways @(NMI or INTM or IntMasked)    if (NMI) IntVect = 18;    else if (~INTM)    begin        if (IntMasked[0])     IntVect = 1;        else if (IntMasked[1]) IntVect = 2;        else if (IntMasked[2]) IntVect = 3;        else if (IntMasked[3]) IntVect = 4;        else if (IntMasked[4]) IntVect = 5;        else if (IntMasked[5]) IntVect = 6;        else if (IntMasked[6]) IntVect = 7;        else if (IntMasked[7]) IntVect = 8;        else if (IntMasked[8]) IntVect = 9;        else if (IntMasked[9]) IntVect = 10;        else if (IntMasked[10]) IntVect = 11;        else if (IntMasked[11]) IntVect = 12;        else if (IntMasked[12]) IntVect = 13;        else if (IntMasked[13]) IntVect = 14;        else if (IntMasked[14]) IntVect = 15;        else IntVect = 0;    end    else IntVect = 0;// Interrupt being processed, sampled with CPU clockalways @(posedge ClockCPU)    if (IntAck | Reset) IntProc <= 0;    else if (IntrStuff | IntWakeSync) IntProc <= 1;// Wakeup from idlealways @(posedge Clock)begin    WakeupSync <= Wakeup;    IntWake <= WakeupSync & ~MemAccEnab;end// Interrupt acknowledge, sampled with CPU clockalways @(posedge ClockCPU or posedge Reset)    if (Reset) IntAck <= 0;    else if (IntrEx) IntAck <= 1;    else IntAck <= 0;// Re-sync IntProc from CPU clockalways @(negedge Clock)    IntProcSync <= IntProc;// Latch interrupt vector and acknowledge flagsalways @(posedge Clock)begin    if (IntrStuffSync | ~(IntProcSync | IntWake)) IntFreeze <= IntVect;    if (IntrExSync)    begin       case (IntFreeze)           0: NIAcks <= 17'b11111111111111111;           1: NIAcks <= 17'b11111111111111110;           2: NIAcks <= 17'b11111111111111101;           3: NIAcks <= 17'b11111111111111011;           4: NIAcks <= 17'b11111111111110111;           5: NIAcks <= 17'b11111111111101111;           6: NIAcks <= 17'b11111111111011111;           7: NIAcks <= 17'b11111111110111111;           8: NIAcks <= 17'b11111111101111111;           9: NIAcks <= 17'b11111111011111111;          10: NIAcks <= 17'b11111110111111111;          11: NIAcks <= 17'b11111101111111111;          12: NIAcks <= 17'b11111011111111111;          13: NIAcks <= 17'b11110111111111111;          14: NIAcks <= 17'b11101111111111111;          15: NIAcks <= 17'b11011111111111111;          16: NIAcks <= 17'b10111111111111111;          18: NIAcks <= 17'b01111111111111111;          default: NIAcks <= 17'b11111111111111111;      endcase    end    else        NIAcks <= 17'b11111111111111111;end// DataRead output muxalways @(IntRegCntrl or NextIMR or NextIFR)    if (IntRegCntrl[2]) DataReadOp = NextIMR;    else DataReadOp = NextIFR;// Read registersassign DataRead = (IntRegCntrl[2] | IntRegCntrl[3]) ? DataReadOp : 16'bZ;assign DataWrite[9] = (RdST0) ? NextINTM : 1'bZ;endmodule