//*******************************************************************       ////IMPORTANT NOTICE                                                          ////================                                                          ////Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  ////This file and associated deliverables are the trade secrets,              ////confidential information and copyrighted works of Mentor Graphics         ////Corporation and its licensors and are subject to your license agreement   ////with Mentor Graphics Corporation.                                         ////                                                                          ////These deliverables may be used for the purpose of making silicon for one  ////IC design only.  No further use of these deliverables for the purpose of  ////making silicon from an IC design is permitted without the payment of an   ////additional license fee.  See your license agreement with Mentor Graphics  ////for further details.  If you have further questions please contact        ////Mentor Graphics Customer Support.                                         ////                                                                          ////This Mentor Graphics core (m320c50eng v1999.010) was extracted on         ////workstation hostid 800059c1 Inventra                                      //// Wait-State Generator// Copyright Mentor Graphics Corporation and Licensors 1998.// V1.105// Revision history// V1.105 - 27 June 1997//          Tri-state drivers removed.// m3s023ct// M320C50 Wait-state generator.// Generates wait states for external program/data/IO accesses.// Combines generated wait-states with external READY input to produce ERDY.//// WaitRegCntrl://    0 : PDWSR write//    1 : IOWSR write//    2 : CWSR write//    3 : PDWSR read//    4 : IOWSR read//    5 : CWSR read//`define C_PDWSR_RESET 16'hFFFF`define C_IOWSR_RESET 16'hFFFF`define C_CWSR_RESET   5'h0Fmodule m3s023ct (FClock, Clock, Reset, READY,//*******************************************************************       ////IMPORTANT NOTICE                                                          ////================                                                          ////Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  ////This file and associated deliverables are the trade secrets,              ////confidential information and copyrighted works of Mentor Graphics         ////Corporation and its licensors and are subject to your license agreement   ////with Mentor Graphics Corporation.                                         ////                                                                          ////These deliverables may be used for the purpose of making silicon for one  ////IC design only.  No further use of these deliverables for the purpose of  ////making silicon from an IC design is permitted without the payment of an   ////additional license fee.  See your license agreement with Mentor Graphics  ////for further details.  If you have further questions please contact        ////Mentor Graphics Customer Support.                                         ////                                                                          ////This Mentor Graphics core (m320c50eng v1999.010) was extracted on         ////workstation hostid 800059c1 Inventra                                      //    DWAddrHi, DWAddrLo, DRAddrHi, DRAddrLo, PAddr,    DWAccess, DRAccess, PAccess, IWAccess, IRAccess, WaitRegCntrl,     MMRWriteData, ERdy, PMMRRdData);    input        FClock, Clock, Reset, READY;    input        DWAccess, DRAccess, PAccess, IWAccess, IRAccess;    input  [5:0] WaitRegCntrl;    input [15:0] MMRWriteData;    input  [2:0] DWAddrHi, DWAddrLo, DRAddrHi, DRAddrLo;    input  [1:0] PAddr;    output [15:0] PMMRRdData;    output        ERdy;    reg [15:0] PDWSR, IOWSR, NextPDWSR, NextIOWSR, PMMRRdData;    reg  [4:0] CWSR, NextCWSR;    wire [2:0] DWCount, DRCount, PCount, IWCount, IRCount;    reg  [2:0] CountVal, WSCount, NextWSCount;    reg        ERdy, CountZero, NextZero;// Registersalways @(Reset or WaitRegCntrl or MMRWriteData or PDWSR or IOWSR or CWSR)begin    if (Reset) NextPDWSR = `C_PDWSR_RESET;    else if (WaitRegCntrl[0]) NextPDWSR = MMRWriteData;    else NextPDWSR = PDWSR;    if (Reset) NextIOWSR = `C_IOWSR_RESET;    else if (WaitRegCntrl[1]) NextIOWSR = MMRWriteData;    else NextIOWSR = IOWSR;    if (Reset) NextCWSR = `C_CWSR_RESET;    else if (WaitRegCntrl[2]) NextCWSR = MMRWriteData[4:0];    else NextCWSR = CWSR;endalways @(posedge Clock)begin    PDWSR <= NextPDWSR;    IOWSR <= NextIOWSR;    CWSR <= NextCWSR;end// Generate wait-states for program, Data and I/O spacem3s054ct U1 (PDWSR, IOWSR, CWSR,  DWAddrHi, DWAddrLo, DRAddrHi, DRAddrLo, PAddr,  PCount, DWCount, DRCount, IWCount, IRCount);// Wait-state load valuealways @(DWCount or DRCount or PCount or IWCount or IRCount  or DWAccess or DRAccess or PAccess or IWAccess or IRAccess)    CountVal = (DWCount & {3{DWAccess}}) |               (DRCount & {3{DRAccess}}) |               (PCount & {3{PAccess}}) |               (IWCount & {3{IWAccess}}) |               (IRCount & {3{IRAccess}});// Wait-state counteralways @(CountZero or CountVal or WSCount)    if (CountZero)        NextWSCount = CountVal;    else        NextWSCount = WSCount - 1;always @(posedge FClock or posedge Reset)    if (Reset)        WSCount <= 0;    else if (Clock)        WSCount <= NextWSCount;// Counter zero detectalways @(NextWSCount)    if (!NextWSCount) NextZero = 1;    else NextZero = 0;always @(posedge FClock or posedge Reset)    if (Reset)        CountZero <= 1;    else if (Clock)        CountZero <= NextZero;// Ready outputalways @(posedge FClock or posedge Reset)    if (Reset)        ERdy <= 1;    else if (Clock)        ERdy <= READY & NextZero;// PMMRRdData output muxalways @(WaitRegCntrl or NextPDWSR or NextIOWSR or NextCWSR)    if (WaitRegCntrl[3]) PMMRRdData = NextPDWSR;    else if (WaitRegCntrl[4]) PMMRRdData = NextIOWSR;    else if (WaitRegCntrl[5]) PMMRRdData = {11'b0,NextCWSR};    else PMMRRdData = 0;endmodule