?? mpc8272.h
字號:
uword picmr1; /* PCI inbound comparison mask */
uword reserved75; /* Reserved area */
uword pitar0; /* PCI inbound translation address */
uword reserved76; /* Reserved area */
uword pibar0; /* PCI inbound base address register 0 */
uword reserved77; /* Reserved area */
uword picmr0; /* PCI inbound comparison mask */
uword reserved78; /* Reserved area */
uword cfg_addr; /* PCI cfg_addr */
uword cfg_data; /* PCI cfg_data */
uword intack; /* PCI int_ack */
uword reserved79[189]; /* Reserved area */
/* ic */
ushort ic_sicr; /* Interrupt Configuration Register */
uchar reserved80[0x2]; /* Reserved area */
uword ic_sivec; /* CP Interrupt Vector Register */
uword ic_sipnr_h; /* Interrupt Pending Register (HIGH) */
uword ic_sipnr_l; /* Interrupt Pending Register (LOW) */
uword ic_siprr; /* SIU Interrupt Priority Register */
uword ic_scprr_h; /* Interrupt Priority Register (HIGH) */
uword ic_scprr_l; /* Interrupt Priority Register (LOW) */
uword ic_simr_h; /* Interrupt Mask Register (HIGH) */
uword ic_simr_l; /* Interrupt Mask Register (LOW) */
uword ic_siexr; /* External Interrupt Control Register */
uchar reserved81[0x58]; /* Reserved area */
/* clocks */
uword clocks_sccr; /* System Clock Control Register */
uchar reserved82[0x4]; /* Reserved area */
uword clocks_scmr; /* System Clock Mode Register */
uchar reserved83[0x4]; /* Reserved area */
uword clocks_rsr; /* Reset Status Register */
uword clocks_rmr; /* Reset Moode Register */
uchar reserved84[0x68]; /* Reserved area */
/* io_ports */
struct io_regs
{
uword pdir; /* Port A-D Data Direction Register */
uword ppar; /* Port A-D Pin Assignment Register */
uword psor; /* Port A-D Special Operation Register */
uword podr; /* Port A-D Open Drain Register */
uword pdat; /* Port A-D Data Register */
uchar reserved85[0xc]; /* Reserved area */
} io_regs[4];
/* cpm_timers */
uchar cpm_timers_tgcr1; /* Timer Global Configuration Register */
uchar reserved86[0x3]; /* Reserved area */
uchar cpm_timers_tgcr2; /* Timer Global Configuration Register */
uchar reserved87[0xb]; /* Reserved area */
ushort cpm_timers_tmr1; /* Timer Mode Register */
ushort cpm_timers_tmr2; /* Timer Mode Register */
ushort cpm_timers_trr1; /* Timer Reference Register */
ushort cpm_timers_trr2; /* Timer Reference Register */
ushort cpm_timers_tcr1; /* Timer Capture Register */
ushort cpm_timers_tcr2; /* Timer Capture Register */
ushort cpm_timers_tcn1; /* Timer Counter */
ushort cpm_timers_tcn2; /* Timer Counter */
ushort cpm_timers_tmr3; /* Timer Mode Register */
ushort cpm_timers_tmr4; /* Timer Mode Register */
ushort cpm_timers_trr3; /* Timer Reference Register */
ushort cpm_timers_trr4; /* Timer Reference Register */
ushort cpm_timers_tcr3; /* Timer Capture Register */
ushort cpm_timers_tcr4; /* Timer Capture Register */
ushort cpm_timers_tcn3; /* Timer Counter */
ushort cpm_timers_tcn4; /* Timer Counter */
ushort cpm_timers_ter[4]; /* Timer Event Register */
uchar reserved88[0x260]; /* Reserved area */
/* sdma general */
uchar sdma_sdsr; /* SDMA Status Register */
uchar reserved89[0x3]; /* Reserved area */
uchar sdma_sdmr; /* SDMA Mask Register */
uchar reserved90[0x3]; /* Reserved area */
/* idma */
uchar reserved91[0x8]; /* Reserved area */
uchar idma_idsr2; /* IDMA Status Register */
uchar reserved93[0x3]; /* Reserved area */
uchar idma_idmr2; /* IDMA Mask Register */
uchar reserved94[0x3]; /* Reserved area */
uchar idma_idsr3; /* IDMA Status Register */
uchar reserved95[0x3]; /* Reserved area */
uchar idma_idmr3; /* IDMA Mask Register */
uchar reserved96[0x2cb]; /* Reserved area */
/* fcc1 */
uword gfmr1; /* FCC General Mode Register */
uword psmr1; /* FCC Protocol Specific Mode Register */
ushort todr1; /* FCC Transmit On Demand Register */
uchar reserved99[0x2]; /* Reserved area */
ushort dsr1; /* FCC Data Sync. Register */
uchar reserved100[0x2]; /* Reserved area */
uword fcce1; /* FCC Event Register */
uword fccm1; /* FCC Mask Register */
uchar fccs1; /* FCC Status Register */
uchar reserved101[0x3]; /* Reserved area */
uchar ftprr0; /* FCC Transmit Partial Rate Register */
uchar ftprr1; /* FCC Transmit Partial Rate Register */
uchar ftprr2; /* FCC Transmit Partial Rate Register */
uchar ftprr3; /* FCC Transmit Partial Rate Register */
/* fcc2 */
uword gfmr2; /* FCC General Mode Register */
uword psmr2; /* FCC Protocol Specific Mode Register */
ushort todr2; /* FCC Transmit On Demand Register */
uchar reserved102[0x2]; /* Reserved area */
ushort dsr2; /* FCC Data Sync. Register */
uchar reserved103[0x2]; /* Reserved area */
uword fcce2; /* FCC Event Register */
uword fccm2; /* FCC Mask Register */
uchar fccs2; /* FCC Status Register */
uchar reserved104[0x47]; /* Reserved area */
/* fcc1 extended registers */
uword firper1; /* FCC1 internal rate port enable */
uword firer1; /* FCC1 internal rate even */
uword firsr1_hi; /* FCC1 internal rate select high */
uword firsr1_lo; /* FCC1 internal rate select low */
uchar gfemr1; /* FCC1 general extended mode ` */
uchar reserved105[0x1f]; /* Reserved area */
/* fcc2 extended registers */
uchar gfemr2; /* FCC2 general extended mode */
uchar reserved106[0x23F]; /* Reserved area */
/* brgs 5-8 */
uword brgs_brgc5; /* BRG Configuration Register */
uword brgs_brgc6; /* BRG Configuration Register */
uword brgs_brgc7; /* BRG Configuration Register */
uword brgs_brgc8; /* BRG Configuration Register */
uchar reserved107[0x260]; /* Reserved area */
/* i2c */
uchar i2c_i2mod; /* IC Mode Register */
uchar reserved108[0x3]; /* Reserved area */
uchar i2c_i2add; /* IC Address Register */
uchar reserved109[0x3]; /* Reserved area */
uchar i2c_i2brg; /* IC BRG Register */
uchar reserved110[0x3]; /* Reserved area */
uchar i2c_i2com; /* IC Command Register */
uchar reserved111[0x3]; /* Reserved area */
uchar i2c_i2cer; /* IC Event Register */
uchar reserved112[0x3]; /* Reserved area */
uchar i2c_i2cmr; /* IC Mask Register */
uchar reserved113[0x14b]; /* Reserved area */
/* cpm */
uword cpm_cpcr; /* Communication Processor Command Register */
uword cpm_rccr; /* RISC Configuration Register */
uword cpm_rmdr; /* RISC Microcode Dev. Support Control Reg. */
ushort cpm_rctr1; /* RISC Controller Trap Register */
ushort cpm_rctr2; /* RISC Controller Trap Register */
ushort cpm_rctr3; /* RISC Controller Trap Register */
ushort cpm_rctr4; /* RISC Controller Trap Register */
uchar reserved114[0x2]; /* Reserved area */
ushort cpm_rter; /* RISC Timers Event Register */
uchar reserved115[0x2]; /* Reserved area */
ushort cpm_rtmr; /* RISC Timers Mask Register */
ushort cpm_rtscr; /* RISC Time-Stamp Timer Control Register */
ushort cpm_rmds; /* RISC Development Support Status Register */
uword cpm_rtsr; /* RISC Time-Stamp Register */
uchar reserved116[0xc]; /* Reserved area */
/* brgs 1-4 */
uword brgs_brgc1; /* BRG Configuration Register */
uword brgs_brgc2; /* BRG Configuration Register */
uword brgs_brgc3; /* BRG Configuration Register */
uword brgs_brgc4; /* BRG Configuration Register */
/* scc */
uword sgsmr_l1; /* SCC General Mode Register */
uword sgsmr_h1; /* SCC General Mode Register */
ushort spsmr1; /* SCC Protocol Specific Mode Register */
uchar reserved117[0x2]; /* Reserved area */
ushort stodr1; /* SCC Transmit-On-Demand Register */
ushort sdsr1; /* SCC Data Synchronization Register */
ushort scce1; /* SCC Event Register */
uchar reserved118[0x2]; /* Reserved area */
ushort sccm1; /* SCC Mask Register */
uchar reserved119; /* Reserved area */
uchar sccs1; /* SCC Status Register */
uchar reserved120[0x28]; /* Reserved area */
struct scc_regs
{
uword sgsmr_l; /* SCC General Mode Register */
uword sgsmr_h; /* SCC General Mode Register */
ushort spsmr; /* SCC Protocol Specific Mode Register */
uchar reserved121[0x2]; /* Reserved area */
ushort stodr; /* SCC Transmit-On-Demand Register */
ushort sdsr; /* SCC Data Synchronization Register */
ushort scce; /* SCC Event Register */
uchar reserved122[0x2]; /* Reserved area */
ushort sccm; /* SCC Mask Register */
uchar reserved123; /* Reserved area */
uchar sccs; /* SCC Status Register */
uchar reserved124[0x8]; /* Reserved area */
} scc_regs[2];
/* smc */
struct smc_regs
{
uchar reserved125[0x2]; /* Reserved area */
ushort smcmr; /* SMC Mode Register */
uchar reserved126[0x2]; /* Reserved area */
uchar smce; /* SMC Event Register */
uchar reserved127[0x3]; /* Reserved area */
uchar smcm; /* SMC Mask Register */
uchar reserved128[0x5]; /* Reserved area */
} smc_regs[2];
/* spi */
ushort spi_spmode; /* SPI Mode Register */
uchar reserved129[0x4]; /* Reserved area */
uchar spi_spie; /* SPI Event Register */
uchar reserved130[0x3]; /* Reserved area */
uchar spi_spim; /* SPI Mask Register */
uchar reserved131[0x2]; /* Reserved area */
uchar spi_spcom; /* SPI Command Register */
uchar reserved132[0x52]; /* Reserved area */
/* cpm_mux */
uchar cpm_mux_cmxsi1cr; /* CPM MUX SI Clock Route Register */
uchar reserved133; /* Reserved area */
uchar cpm_mux_cmxsi2cr; /* CPM MUX SI Clock Route Register */
uchar reserved134; /* Reserved area */
uword cpm_mux_cmxfcr; /* CPM MUX FCC Clock Route Register */
uword cpm_mux_cmxscr; /* CPM MUX SCC Clock Route Register */
uchar cpm_mux_cmxsmr; /* CPM MUX SMC Clock Route Register */
uchar reserved135; /* Reserved area */
ushort cpm_mux_cmxuar; /* CPM MUX VUTOPIA Address Register */
uchar reserved136[0x30]; /* Reserved area */
/* si */
ushort sixmr[2]; /* SI TDM Mode Registers A & B */
uchar reserved137[0x3]; /* Reserved area */
uchar sigmr; /* SI Global Mode Register */
uchar reserved138; /* Reserved area */
uchar sicmdr; /* SI Command Register */
uchar reserved139; /* Reserved area */
uchar sistr; /* SI Status Register */
uchar reserved140[0x2]; /* Reserved area */
ushort sirsr; /* SI RAM Shadow Address Register */
uchar reserved144[0x10]; /* Reserved area */
/* usb */
uchar usmod; /* USB mode register */
uchar usadr; /* USB address register */
uchar uscom; /* USB command register */
uchar reserved145[0x1];
ushort usep1; /* USB endpoint 0 register */
ushort usep2; /* USB endpoint 1 register */
ushort usep3; /* USB endpoint 2 register */
ushort usep4; /* USB endpoint 3 register */
uchar reserved146[0x4]; /* Reserved area */
ushort usber; /* USB event register */
uchar reserved147[0x2]; /* Reserved area */
ushort usbmr; /* USB mask register */
uchar reserved148[0x1]; /* Reserved area */
uchar usbs; ?? 快捷鍵說明
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