// 11 wait states
   // timinig relax
   //-------------------------------------------------------------------------

   addis    r5,0,0xFF80     // R5 holds the value temporarily
   ori      r5,r5,0x0876   

   //------------------------------------------------------------------------
   // It's important to note the order in which OR0 and BR0 are programmed.
   // When coming out of reset and CS0 is the global chip select, OR0 MUST be 
   // programmed AFTER BR0. In all other cases BRx would be programmed after
   // ORx.
   //------------------------------------------------------------------------

   //------------------
   // Write the values
   //------------------
   stw        r3,BR0(r4)
   stw        r5,OR0(r4)



// init BCSR

   //-------------------------------------------------------------------------
   // Base Register 1 (BR1): Bank 1 is assigned to the Board Control and
   //                        Status Registers (BCSRs). 
   // BA (Base Address) = 0x0450+0b for a total of 17 address bits. This value
   //                     represents the upper 17 bits of the base address.
   // Bits 17-18 reserved. = 00
   // PS (Port Size) = 11b = 32 bit port size
   // DECC (Data Error Correction and Checking) = 00 = Data errors checking
   //                                                  Disabled.
   // WP (Write Protect) = 0 = both read and write accesses are allowed
   // MS (Machine Select) = 000 = General Purpose Chip Select Machine (GPCM)
   //                             for 60x bus Selected
   // EMEMC (External Memory Controller Enable) = 0 = Accesses are handled by
   //                                                 the memory controller
   //                                                 according to MSEL.
   // ATOM (Atomic Operation) = 00 = The address space controlled by the 
   //                                memory controller bank is not used for
   //                                atomic operations.
   // DR (Delayed Read) = 0 = Normal operation.
   // V (Valid Bit) =  1 = Valid bit set
   //-------------------------------------------------------------------------

   addis    r3,0,0x0450     // R3 holds the value temporarily
   ori      r3,r3,0x1801

   //-------------------------------------------------------------------------
   // Option Register 1 (OR1) for GPCM use: further BCSR definitions
   // AM (Address Mask) = 0xFFFF +1b = We've masked the upper 17 bits which 
   //                                  which defines a 32 Kbyte memory block.
   // Bits 17-19 Reserved - set to 000.
   // CSNT (Chip Select Negation Time) = 0 = CS/|WE/ are negated normally.
   // ACS (Address To Chip-Select Setup) = 00 = CS/ is output at the same 
   //                                           time as the addr lines.
   // Bit 23 Reserved - set to 0.
   // SCY (Cycle Length In Clocks) = 0001 = Add a 1 clock cycle wait state
   // SETA (External Transfer Acknowledge) = 0 = PSDVAL/ is generated 
   //                                            internally by the memory 
   //                                            controller unless GTA/ is 
   //                                            asserted earlier externally.
   // TRLX (Timing Relaxed) = 0 = Normal timing is generated by the GPCM.
   // EHTR (Extended Hold Time On Read Accesses) = 0 = Normal timing is 
   //                                                  generated by the memory
   //                                                  controller
   // Bit 31 Reserved - set to 0.
   //-------------------------------------------------------------------------

   addis    r5,0,0xFFFF     // R5 holds the value temporarily
   ori      r5,r5,0x8010

   //------------------
   // Write the values
   //------------------

   stw        r5,OR1(r4)
   stw        r3,BR1(r4)


   // PCI init
   addis    r3,0,0x0473     // R3 holds the value temporarily
   ori      r3,r3,0x1801

   addis    r5,0,0xFFFF     // R5 holds the value temporarily
   ori      r5,r5,0x8010

   stw        r5,OR3(r4)
   stw        r3,BR3(r4)


   //-------------------------------------------------------------------------
   // Program the 60x Bus Assigned SDRAM Refresh Timer (PSRT).
   //-------------------------------------------------------------------------

   addi     r5,0,0x0013      // load 0x13 or 19 
   stb      r5,PSRT(r4)      // store byte - bits[24-31]


   //########################
   // Program Bank Registers
   //########################


   //-------------------------------------------------------------------------
   // Base Register 2 (BR2): Bank 2 is assigned to the 32 Mbyte SDRAM (2 banks) memory
   //                        that resides on the 60x Bus. The 
   //                        particulars are defined here. 
   //
   // - BA (Base Address) = 0x0000+0b for a total of 17 address bits. This 
   //                       value represents the upper 17 bits of the base 
   //                       address.
   // - Bits 17-18 reserved. = 00 = cleared to 0.
   // - PS (Port Size) = 00b = 64 bit port size
   // - DECC (Data Error Correction and Checking) = 00 = Data errors checking
   //                                                    Disabled.
   // - WP (Write Protect) = 0 = both read and write accesses are allowed
   // - MS (Machine Select) = 010 = SDRAM Machine for 60x bus Selected
   // - EMEMC (External Memory Controller Enable) = 0 = 
   //    Accesses are handled by the memory controller according to MSEL.
   // - ATOM (Atomic Operation) = 00 = The address space controlled by the 
   //                                  memory controller bank is not used for
   //                                  atomic operations.
   // - DR (Delayed Read) = 0 = Normal operation.
   // - V (Valid Bit) =  1 = Valid bit set
   //-------------------------------------------------------------------------

   addis    r3,0,0x0000     // R3 holds the value temporarily
   ori      r3,r3,0x0041

   //-------------------------------------------------------------------------
   // Option Register 2 (OR2) for SDRAM Machine use: further SDRAM definitions
   //
   // 32MByte block size
   // 4 banks per device
   // row starts at A7
   // 12 row lines
   // internal bank interleaving allowed
   // normal AACK operation
   //-------------------------------------------------------------------------

   addis    r5,0,0xFC00     // R5 holds the value temporarily
   ori      r5,r5,0x2CC0

   //------------------
   // Write the values
   //------------------

   stw        r5,OR2(r4)
   stw        r3,BR2(r4)


   //#############################################
   // Perform Initialization sequence to 60x SDRAM
   //#############################################

   //-------------------------------------------------------------------------
   // Program the PowerPC SDRAM Mode Registr (PSDMR). This register is used
   // to configure operations pertaining to SDRAM. Program the PSDMR, turning 
   // off refresh services and changing the SDRAM operation to "Precharge all
   // banks". Then do a single write to an arbitrary location. Writing 0xFF 
   // to address 0 will do the trick.
   //
   // page based interleaving
   // refresh enabled
   // normal operation mode
   // address muxing mode 2, A14-16 on BNKSEL, A8 on PSDA 10,
   // 8 clocks refresh recovery
   // 3 clocks precharge to activate delay
   // 3 clocks to activate r/w delay
   // 4 beat burst length
   // 2 clock write recovery time
   // no extra cycle on address phase
   // normal timing for control lines
   // 3 clocks CAS latency
   //-------------------------------------------------------------------------

   addis    r0,0,0           // Load 0 into r0
   
   addi     r6,0,0x0000      // Load 0x00000000 into r6

   addis    r3,0,0x834F
   ori      r3,r3,0x36A3
   stw      r3,PSDMR(r4)	// Precharge all banks

   addis    r3,0,0xAB4F
   ori      r3,r3,0x36A3
   stw      r3,PSDMR(r4)	// Precharge all banks

   sync
   stb      r6,0(r0)         // Write 0x00 to address 0 - bits [24-31]


   //-------------------------------------------------------------------------
   // Program the PSDMR keeping refresh services off and changing the
   // SDRAM operation to "CBR Refresh". This step is responsible for issuing
   // a minimum of 8 auto-refresh commands. This is done by the SDRAM machine
   // by issuing the CBR Refresh command by programming the OP field of the 
   // PSDMR register and writing 0xFF 8 times to an arbitrary address.
   //-------------------------------------------------------------------------
   
   addis    r3,0,0x8B4F
   ori      r3,r3,0x36A3
   stw      r3,PSDMR(r4)	// CBR Refresh

   //------------------------------------------
   // Loop 8 times, writing 0xFF to address 0
   //------------------------------------------

   addi  r6,0,0x0008
   mtspr CTR,r6             // Load CTR with 8. The CTR special purpose
                            // is spr 9

   addi  r3,0,0x00FF      // Load 0x000000FF into r3
   sync

write_loop1:

   stb   r3,0(r0)         // Write 0xFF to address 0 - bits [24-31]
    
   bc    16,0,write_loop1  // Decrement CTR, then branch if the decremented CTR
                          // is not equal to 0      

   //-------------------------------------------------------------------------
   // Program the PSDMR again turning off refresh services and changing the
   // SDRAM operation to "Mode Register Write". Then do a single write to an
   // arbitrary location. The various fields that will be programmed in the 
   // mode register on the SDRAM were specified in fields of the PSDMR, like
   // the BR (burst length) and the CL (CAS Latency) field.
   //-------------------------------------------------------------------------
   
   addis    r3,0,0x9B4F
   ori      r3,r3,0x36A3
   stw      r3,PSDMR(r4)

   addi     r3,0,0x0000      // Load 0x00000000 into r3
   ori		r0, r0, 0x0190	 // Change address from 0x00000000 -> 0x00000190
   sync
   stb      r3,0(r0)         // Write 0xFF to address 0x00000190 - bits [24-31]
 
   //-------------------------------------------------------------------------
   // Program the PSDMR one last time turning on refresh services and changing 
   // the SDRAM operation to "Normal Operation". 
   //-------------------------------------------------------------------------
   
   addis    r3,0,0xC34F
   ori      r3,r3,0x36A3
   stw      r3,PSDMR(r4)



   //######################################################
   // There is no SDRAM when the Local Bus work in PCI mode
   //######################################################

   addi     r5,0,0x0000      // load 0x0 
   stb      r5,LSRT(r4)      // store byte - bits[24-31]







// init PCI registers

// PCI General Control Register
   addis    r3,0,0x0100
   ori      r3,r3,0x0000
   stw      r3,PCI_GCR(r4)

// Two pairs of new registers have been added to the SIU to detect accesses from side to the
// PCI bridge (other than PCI internal registers accesses). Each pair consists of a PCI base
// register (PCIBRx) for comparing addresses and a corresponding PCI mask register
// (PCIMSKx). 
   addis    r3,0,0xFF80 
   ori      r3,r3,0x0000
   stw      r3,PCIMSK0(r4)

   addis    r3,0,0x0480
   ori      r3,r3,0x0001
   stw      r3,PCIBR0(r4)

   addis    r3,0,0xC000 
   ori      r3,r3,0x0000
   stw      r3,PCIMSK1(r4)

   addis    r3,0,0x8000
   ori      r3,r3,0x0001
   stw      r3,PCIBR1(r4)

   addis    r3,0,0x3012
   ori      r3,r3,0x6754
   stw      r3,PPC_ALRH(r4)

   addi     r3,0,0x0003
   stb      r3,PPC_ACR(r4)

   // Security Co-Processor (SEC) configuration

   //program SEC Mask Register with value 0xFFFE0000 - 128 KB memory space
   addis    r3,0,0xFFFE
   ori      r3,r3,0x0000 
   stw      r3,SECMR(r4)
   // program SEC Base Register - IMMR + 0x40000
   mfspr    r5, 311
   addis    r3,r5,0x0004
   ori      r3,r3,0x0001
   stw      r3,SECBR(r4)


////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// Copy the exception vectors from ROM to RAM
//
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
	
	lis			r3, gInterruptVectorTable@h
	ori			r3, r3, gInterruptVectorTable@l
	subi		r3,r3,0x0004
	
	lis			r4, gInterruptVectorTableEnd@h
	ori			r4, r4, gInterruptVectorTableEnd@l
	
	lis			r5, 0xFFFF
	ori			r5,r5,0xFFFC
	
loop:
	lwzu		r6, 4(r3)
	stwu		r6, 4(r5)
	
	cmpw		r3,r4
	blt			loop
#endif //ROM_version
	
#ifdef CACHE_VERSION
	mfspr    r6,LR        // Save the Link Register value. The link register's
                          // value will be restored so that this function 
                          // can return to the calling address.
	bl		mmu_cache_init
	mtspr    LR,r6      // restore original Link Register value 
#endif
  
   blr 
}