?? netlist.txt
字號:
SIGNAL_MODEL 'N74F393D'; 'U1' 'U4'
SIGNAL_MODEL 'CAP_1UF'; 'C9' 'C10' 'C11' 'C12' 'C13' 'C14',
'C15' 'C16'
$NETS
$A_PROPERTIES
LOGICAL_PATH '@design_lib.ps0(sch_1):a(1)'; 'A1'
LOGICAL_PATH '@design_lib.ps0(sch_1):a(11)'; 'A11'
LOGICAL_PATH '@design_lib.ps0(sch_1):a(13)'; 'A13'
LOGICAL_PATH '@design_lib.ps0(sch_1):a(15)'; 'A15'
LOGICAL_PATH '@design_lib.ps0(sch_1):a(17)'; 'A17'
LOGICAL_PATH '@design_lib.ps0(sch_1):a(19)'; 'A19'
LOGICAL_PATH '@design_lib.ps0(sch_1):a(20)'; 'A20'
LOGICAL_PATH '@design_lib.ps0(sch_1):a(22)'; 'A22'
LOGICAL_PATH '@design_lib.ps0(sch_1):a(3)'; 'A3'
LOGICAL_PATH '@design_lib.ps0(sch_1):a(5)'; 'A5'
LOGICAL_PATH '@design_lib.ps0(sch_1):a(7)'; 'A7'
NET_SPACING_TYPE 'ABUS'; 'A9' 'A8' 'A7' 'A6' 'A5' 'A4',
'A3' 'A23' 'A22' 'A21' 'A20' 'A2',
'A19' 'A18' 'A17' 'A16' 'A15' 'A14',
'A13' 'A12' 'A11' 'A10' 'A1'
LOGICAL_PATH '@design_lib.ps0(sch_1):a(9)'; 'A9'
BUS_NAME '@DESIGN_LIB.PS0(SCH_1):ADDR'; 'ADDR7' 'ADDR6' 'ADDR5' 'ADDR4' 'ADDR3' 'ADDR2',
'ADDR1' 'ADDR0'
LOGICAL_PATH '@design_lib.ps0(sch_1):addr(7)'; 'ADDR7'
TOPOLOGY_TEMPLATE_MAPPING_MODE 'PINUSE_REFDES'; 'ADDR7' 'ADDR6' 'ADDR5' 'ADDR4' 'ADDR3' 'ADDR2',
'ADDR1' 'ADDR0'
TOPOLOGY_TEMPLATE_REVISION '1.0'; 'ADDR7' 'ADDR6' 'ADDR5' 'ADDR4' 'ADDR3' 'ADDR2',
'ADDR1' 'ADDR0'
TOPOLOGY_TEMPLATE 'mrd'; 'ADDR7' 'ADDR6' 'ADDR5' 'ADDR4' 'ADDR3' 'ADDR2',
'ADDR1' 'ADDR0'
ASSIGN_TOPOLOGY 'MRD.TOP:PINUSE_REFDES'; 'ADDR7' 'ADDR6' 'ADDR5' 'ADDR4' 'ADDR3' 'ADDR2',
'ADDR1' 'ADDR0'
LOGICAL_PATH '@design_lib.ps0(sch_1):adsl'; 'ADSL'
LOGICAL_PATH '@design_lib.ps0(sch_1):blel'; 'BLEL'
LOGICAL_PATH '@design_lib.ps0(sch_1):cas1l'; 'CAS1L'
LOGICAL_PATH '@design_lib.ps0(sch_1):clrcnt'; 'CLRCNT'
LOGICAL_PATH '@design_lib.ps0(sch_1):d(0)'; 'D0'
LOGICAL_PATH '@design_lib.ps0(sch_1):d(1)'; 'D1'
LOGICAL_PATH '@design_lib.ps0(sch_1):d(10)'; 'D10'
LOGICAL_PATH '@design_lib.ps0(sch_1):d(11)'; 'D11'
LOGICAL_PATH '@design_lib.ps0(sch_1):d(12)'; 'D12'
LOGICAL_PATH '@design_lib.ps0(sch_1):d(13)'; 'D13'
LOGICAL_PATH '@design_lib.ps0(sch_1):d(14)'; 'D14'
LOGICAL_PATH '@design_lib.ps0(sch_1):d(15)'; 'D15'
LOGICAL_PATH '@design_lib.ps0(sch_1):d(2)'; 'D2'
LOGICAL_PATH '@design_lib.ps0(sch_1):d(3)'; 'D3'
LOGICAL_PATH '@design_lib.ps0(sch_1):d(4)'; 'D4'
LOGICAL_PATH '@design_lib.ps0(sch_1):d(5)'; 'D5'
LOGICAL_PATH '@design_lib.ps0(sch_1):d(6)'; 'D6'
LOGICAL_PATH '@design_lib.ps0(sch_1):d(7)'; 'D7'
LOGICAL_PATH '@design_lib.ps0(sch_1):d(8)'; 'D8'
BUS_NAME '@DESIGN_LIB.PS0(SCH_1):D'; 'D9' 'D8' 'D7' 'D6' 'D5' 'D4',
'D3' 'D2' 'D15' 'D14' 'D13' 'D12',
'D11' 'D10' 'D1' 'D0'
LOGICAL_PATH '@design_lib.ps0(sch_1):data(1)'; 'DATA1'
LOGICAL_PATH '@design_lib.ps0(sch_1):data(11)'; 'DATA11'
LOGICAL_PATH '@design_lib.ps0(sch_1):data(13)'; 'DATA13'
LOGICAL_PATH '@design_lib.ps0(sch_1):data(15)'; 'DATA15'
LOGICAL_PATH '@design_lib.ps0(sch_1):data(3)'; 'DATA3'
LOGICAL_PATH '@design_lib.ps0(sch_1):data(5)'; 'DATA5'
LOGICAL_PATH '@design_lib.ps0(sch_1):data(7)'; 'DATA7'
BUS_NAME '@DESIGN_LIB.PS0(SCH_1):DATA'; 'DATA9' 'DATA8' 'DATA7' 'DATA6' 'DATA5' 'DATA4',
'DATA3' 'DATA2' 'DATA15' 'DATA14' 'DATA13' 'DATA12',
'DATA11' 'DATA10' 'DATA1' 'DATA0'
LOGICAL_PATH '@design_lib.ps0(sch_1):hlda'; 'HLDA'
LOGICAL_PATH '@design_lib.ps0(sch_1):page1_i121@design_lib.addr_mux(sch_1):i3(0)'; 'I30'
LOGICAL_PATH '@design_lib.ps0(sch_1):page1_i121@design_lib.addr_mux(sch_1):i3(1)'; 'I31'
LOGICAL_PATH '@design_lib.ps0(sch_1):page1_i121@design_lib.addr_mux(sch_1):i3(2)'; 'I32'
LOGICAL_PATH '@design_lib.ps0(sch_1):page1_i121@design_lib.addr_mux(sch_1):i3(3)'; 'I33'
LOGICAL_PATH '@design_lib.ps0(sch_1):page1_i121@design_lib.addr_mux(sch_1):i3(4)'; 'I34'
LOGICAL_PATH '@design_lib.ps0(sch_1):page1_i121@design_lib.addr_mux(sch_1):i3(5)'; 'I35'
LOGICAL_PATH '@design_lib.ps0(sch_1):page1_i121@design_lib.addr_mux(sch_1):i3(6)'; 'I36'
BUS_NAME '@DESIGN_LIB.PS0(SCH_1):P_UPREV5'; 'I37' 'I36' 'I35' 'I34' 'I33' 'I32',
'I31' 'I30'
LOGICAL_PATH '@design_lib.ps0(sch_1):muxs0l'; 'MUXS0L'
ROUTE_PRIORITY '1'; 'PCLK' 'CLK2' 'ADDR7' 'ADDR6' 'ADDR5' 'ADDR4',
'ADDR3' 'ADDR2' 'ADDR1' 'ADDR0'
NET_SPACING_TYPE 'CLOCKS'; 'PCLK' 'CLK2'
NET_PHYSICAL_TYPE 'CLOCKS'; 'PCLK' 'CLK2'
LOGICAL_PATH '@design_lib.ps0(sch_1):pclk'; 'PCLK'
LOGICAL_PATH '@design_lib.ps0(sch_1):ra(0)'; 'RA0'
LOGICAL_PATH '@design_lib.ps0(sch_1):ra(1)'; 'RA1'
LOGICAL_PATH '@design_lib.ps0(sch_1):ra(2)'; 'RA2'
LOGICAL_PATH '@design_lib.ps0(sch_1):ra(3)'; 'RA3'
LOGICAL_PATH '@design_lib.ps0(sch_1):ra(4)'; 'RA4'
LOGICAL_PATH '@design_lib.ps0(sch_1):ra(5)'; 'RA5'
LOGICAL_PATH '@design_lib.ps0(sch_1):ra(6)'; 'RA6'
BUS_NAME '@DESIGN_LIB.PS0(SCH_1):RA'; 'RA7' 'RA6' 'RA5' 'RA4' 'RA3' 'RA2',
'RA1' 'RA0'
LOGICAL_PATH '@design_lib.ps0(sch_1):rasl'; 'RASL'
LOGICAL_PATH '@design_lib.ps0(sch_1):ref'; 'REF'
LOGICAL_PATH '@design_lib.ps0(sch_1):resetl'; 'RESETL'
LOGICAL_PATH '@design_lib.ps0(sch_1):unnamed_1_27c256_37p_vpp'; 'UNNAMED_1_27C256_37P_VPP'
LOGICAL_PATH '@design_lib.ps0(sch_1):unnamed_1_f32_115p_a'; 'UNNAMED_1_F32_115P_A'
LOGICAL_PATH '@design_lib.ps0(sch_1):wel'; 'WEL'
DIFFERENTIAL_PAIR 'DIFFPAIR1'; 'AB+' 'AB-'
DIFFERENTIAL_PAIR 'DIFFPAIR2'; 'CD+' 'CD-'
NET_PHYSICAL_TYPE 'DIFF_PAIRS'; 'CD+' 'CD-' 'AB+' 'AB-'
NET_SPACING_TYPE 'DIFF_PAIRS'; 'CD+' 'CD-' 'AB+' 'AB-'
ELECTRICAL_CONSTRAINT_SET 'UPREVED_DEFAULT'; 'CD+' 'CD-' 'AB+' 'AB-' 'W_R' 'WEL',
'UNNAMED_1_F393_30P_Q' 'UNNAMED_1_F32_115P_A' 'UNNAMED_1_F109_10P_CL' 'UNNAMED_1_27C256_37P_VPP' 'ROMOEL' 'RESETL',
'RESET' 'REF' 'RDYL' 'RASL' 'RA7' 'RA6',
'RA5' 'RA4' 'RA3' 'RA2' 'RA1' 'RA0',
'PCLK' 'M_IO' 'MUXS0L' 'I37' 'I36' 'I35',
'I34' 'I33' 'I32' 'I31' 'I30' 'HLDA',
'DATA9' 'DATA8' 'DATA7' 'DATA6' 'DATA5' 'DATA4',
'DATA3' 'DATA2' 'DATA15' 'DATA14' 'DATA13' 'DATA12',
'DATA11' 'DATA10' 'DATA1' 'DATA0' 'D9' 'D8',
'D7' 'D6' 'D5' 'D4' 'D3' 'D2',
'D15' 'D14' 'D13' 'D12' 'D11' 'D10',
'D1' 'D0' 'CLRCNT' 'CAS1L' 'CAS0L' 'BLEL',
'BHEL' 'ADSL' 'A9' 'A8' 'A7' 'A6',
'A5' 'A4' 'A3' 'A23' 'A22' 'A21',
'A20' 'A2' 'A19' 'A18' 'A17' 'A16',
'A15' 'A14' 'A13' 'A12' 'A11' 'A10',
'A1' 'VSS' 'GND' 'VCC'
IMPEDANCE_RULE 'ALL:ALL:75 ohm:2 %'; 'CD+' 'CD-' 'AB+' 'AB-'
LOGICAL_PATH '@design_lib.ps0(sch_1):w_r'; 'W_R'
LOGICAL_PATH '@design_lib.ps0(sch_1):unnamed_1_osc_1p_b'; 'UNNAMED_1_OSC_1P_B'
LOGICAL_PATH '@design_lib.ps0(sch_1):unnamed_1_f393_30p_q'; 'UNNAMED_1_F393_30P_Q'
LOGICAL_PATH '@design_lib.ps0(sch_1):unnamed_1_f109_10p_cl'; 'UNNAMED_1_F109_10P_CL'
LOGICAL_PATH '@design_lib.ps0(sch_1):romoel'; 'ROMOEL'
LOGICAL_PATH '@design_lib.ps0(sch_1):reset'; 'RESET'
LOGICAL_PATH '@design_lib.ps0(sch_1):rdyl'; 'RDYL'
LOGICAL_PATH '@design_lib.ps0(sch_1):ra(7)'; 'RA7'
RELATIVE_PROPAGATION_DELAY 'M9:G:L:S:0 ns:0.2 ns'; 'PCLK'
LOGICAL_PATH '@design_lib.ps0(sch_1):m_io'; 'M_IO'
LOGICAL_PATH '@design_lib.ps0(sch_1):page1_i121@design_lib.addr_mux(sch_1):i3(7)'; 'I37'
ROUTE_PRIORITY '2'; 'DATA9' 'DATA8' 'DATA7' 'DATA6' 'DATA5' 'DATA4',
'DATA3' 'DATA2' 'DATA15' 'DATA14' 'DATA13' 'DATA12',
'DATA11' 'DATA10' 'DATA1' 'DATA0'
LOGICAL_PATH '@design_lib.ps0(sch_1):data(9)'; 'DATA9'
NET_PHYSICAL_TYPE 'DATA'; 'DATA9' 'DATA8' 'DATA7' 'DATA6' 'DATA5' 'DATA4',
'DATA3' 'DATA2' 'DATA15' 'DATA14' 'DATA13' 'DATA12',
'DATA11' 'DATA10' 'DATA1' 'DATA0'
NET_SPACING_TYPE 'DATA'; 'DATA9' 'DATA8' 'DATA7' 'DATA6' 'DATA5' 'DATA4',
'DATA3' 'DATA2' 'DATA15' 'DATA14' 'DATA13' 'DATA12',
'DATA11' 'DATA10' 'DATA1' 'DATA0'
LOGICAL_PATH '@design_lib.ps0(sch_1):data(8)'; 'DATA8'
LOGICAL_PATH '@design_lib.ps0(sch_1):data(6)'; 'DATA6'
LOGICAL_PATH '@design_lib.ps0(sch_1):data(4)'; 'DATA4'
LOGICAL_PATH '@design_lib.ps0(sch_1):data(2)'; 'DATA2'
LOGICAL_PATH '@design_lib.ps0(sch_1):data(14)'; 'DATA14'
LOGICAL_PATH '@design_lib.ps0(sch_1):data(12)'; 'DATA12'
LOGICAL_PATH '@design_lib.ps0(sch_1):data(10)'; 'DATA10'
LOGICAL_PATH '@design_lib.ps0(sch_1):data(0)'; 'DATA0'
LOGICAL_PATH '@design_lib.ps0(sch_1):d(9)'; 'D9'
LOGICAL_PATH '@design_lib.ps0(sch_1):clk2'; 'CLK2'
LOGICAL_PATH '@design_lib.ps0(sch_1):cas0l'; 'CAS0L'
LOGICAL_PATH '@design_lib.ps0(sch_1):bhel'; 'BHEL'
LOGICAL_PATH '@design_lib.ps0(sch_1):addr(6)'; 'ADDR6'
LOGICAL_PATH '@design_lib.ps0(sch_1):addr(5)'; 'ADDR5'
LOGICAL_PATH '@design_lib.ps0(sch_1):addr(4)'; 'ADDR4'
LOGICAL_PATH '@design_lib.ps0(sch_1):addr(3)'; 'ADDR3'
LOGICAL_PATH '@design_lib.ps0(sch_1):addr(2)'; 'ADDR2'
LOGICAL_PATH '@design_lib.ps0(sch_1):addr(1)'; 'ADDR1'
LOGICAL_PATH '@design_lib.ps0(sch_1):addr(0)'; 'ADDR0'
BUS_NAME '@DESIGN_LIB.PS0(SCH_1):A'; 'A9' 'A8' 'A7' 'A6' 'A5' 'A4',
'A3' 'A23' 'A22' 'A21' 'A20' 'A2',
'A19' 'A18' 'A17' 'A16' 'A15' 'A14',
'A13' 'A12' 'A11' 'A10' 'A1'
LOGICAL_PATH '@design_lib.ps0(sch_1):a(8)'; 'A8'
LOGICAL_PATH '@design_lib.ps0(sch_1):a(6)'; 'A6'
LOGICAL_PATH '@design_lib.ps0(sch_1):a(4)'; 'A4'
LOGICAL_PATH '@design_lib.ps0(sch_1):a(23)'; 'A23'
LOGICAL_PATH '@design_lib.ps0(sch_1):a(21)'; 'A21'
LOGICAL_PATH '@design_lib.ps0(sch_1):a(2)'; 'A2'
LOGICAL_PATH '@design_lib.ps0(sch_1):a(18)'; 'A18'
LOGICAL_PATH '@design_lib.ps0(sch_1):a(16)'; 'A16'
LOGICAL_PATH '@design_lib.ps0(sch_1):a(14)'; 'A14'
LOGICAL_PATH '@design_lib.ps0(sch_1):a(12)'; 'A12'
LOGICAL_PATH '@design_lib.ps0(sch_1):a(10)'; 'A10'
NO_RAT; 'VSS'
NO_RAT; 'GND'
NO_RAT; 'VCC'
VOLTAGE '5.0'; 'VSS' 'VCC'
VOLTAGE '0.0'; 'GND'
MIN_LINE_WIDTH '12 MIL'; 'GND' 'VCC'
LOGICAL_PATH '@design_lib.glbl(ps0_cfg_package):gnd'; 'GND'
LOGICAL_PATH '@design_lib.glbl(ps0_cfg_package):vcc'; 'VCC'
$END
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