?? dbotx.c
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/*********************************************************************
* Filename: DBOTX.c
*
* Description: Illustrates the operation of DBO field for a Transmit mailbox.
* Mailbox 11 is used in this example
*
* Last update: 12/24/2002
*********************************************************************/
#include "DSP28_Device.h"
void error(int);
long i;
void InitECan(void);
main()
{
/* Create a shadow register structure for the CAN control registers. This is
needed, since, only 32-bit access is allowed to these registers. 16-bit access
to these registers could potentially corrupt the register contents. This is
especially true while writing to a bit (or group of bits) among bits 16 - 31 */
struct ECAN_REGS ECanaShadow;
/* Initialize the CAN module */
InitECan();
/* Write to the MSGID field */
ECanaMboxes.MBOX11.MSGID.all = 0x80000011; // Ext Identifier (ID = 11)
/* Configure Mailbox under test as a Transmit mailbox */
ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;
ECanaShadow.CANMD.bit.MD11 = 0;
ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;
/* Enable Mailbox under test */
ECanaShadow.CANME.all = ECanaRegs.CANME.all;
ECanaShadow.CANME.bit.ME11 = 1;
ECanaRegs.CANME.all = ECanaShadow.CANME.all;
/* Write to Master Control reg */
ECanaMboxes.MBOX11.MCF.bit.DLC = 8;
/* Write to the mailbox RAM field using 16-bit writes */
ECanaMboxes.MBOX11.MDRL.bit.LOW_WORD = 0x0201;
ECanaMboxes.MBOX11.MDRL.bit.HI_WORD = 0x0403;
ECanaMboxes.MBOX11.MDRH.bit.LOW_WORD = 0x0605;
ECanaMboxes.MBOX11.MDRH.bit.HI_WORD = 0x0807;
/* Configure DBO bit */
ECanaRegs.CANMC.bit.DBO = 1; // See Note 2
/* Begin transmitting */
ECanaShadow.CANTRS.all = 0; // Set TRS bit
ECanaShadow.CANTRS.bit.TRS11 = 1;
ECanaRegs.CANTRS.all = ECanaShadow.CANTRS.all;
while(ECanaRegs.CANTA.bit.TA11 == 0 ) {} // Wait for TA11 bit to be set..
ECanaShadow.CANTA.all = 0; // See Note 1
ECanaShadow.CANTA.bit.TA11 = 1; // Clear TA11
ECanaRegs.CANTA.all = ECanaShadow.CANTA.all;
asm(" ESTOP0");
}
/*
Note 1: Initialize the "shadow-TA register" to zero before setting any bit(s)
in order to clear it (them) in the TA register. Otherwise, some other TAn bit(s)
that is (are) set could be inadvertently cleared.
Note 2: Following is the effect of DBO bit
Let the mailbox RAM contents be as follows...
615C: 0201
615D: 0403
615E: 0605
615F: 0807
When DBO = 1, the bytes will be transmitted in the following sequence:
01 02 03 04 05 06 07 08
When DBO = 0, the bytes will be transmitted in the following sequence:
04 03 02 01 08 07 06 05
CANalyzer configuration file: 1M80spRx.cfg
*/
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