Data Cycle.</FONT></CENTER></TD>
            <TD><B>1. Data is placed on Data lines by Host.</B><BR>2. Host 
              then indicates a Data Cycle will proceed by asserting 
              HostAck.<BR><B>3. Host indicates valid data by asserting HostClk 
              low.</B><BR>4. Peripheral sends its acknowledgment of valid data 
              by asserting PeriphAck.<BR><B>5. Host de-asserts HostClk high. +ve 
              edge used to shift data into the Peripheral.</B><BR>6. Peripheral 
              sends it's acknowledgment of the byte via de-asserting PeriphAck. 
            </TD></TR></TBODY></TABLE></CENTER><BR><A name=5><I><FONT size=+2>ECP 
        Forward Command Cycle</FONT></I></A> 
        <HR>
        <BR>
        <CENTER>
        <TABLE border=0>
          <TBODY>
          <TR>
            <TD><IMG alt="Enhanced Capabilities Port Forward Command Cycle" 
              src="Interfacing the Extended Capabilities Port.files/ecpfcomm.gif" 
              border=0> <BR>
              <CENTER><FONT size=-1>Figure 2. Enhanced Capabilities Port Forward 
              Command Cycle.</FONT></CENTER></TD>
            <TD><B>1. Data is placed on Data lines by Host.</B><BR>2. Host 
              then indicates a Command cycle will proceed by de-asserting 
              HostAck.<BR><B>3. Host indicates valid data by asserting HostClk 
              low.</B><BR>4. Peripheral sends its acknowledgment of valid data 
              by asserting PeriphAck.<BR><B>5. Host de-asserts HostClk high. +ve 
              edge used to shift data into the Peripheral.</B><BR>6. Peripheral 
              sends it's acknowledgment of the byte via de-asserting PeriphAck. 
            </TD></TR></TBODY></TABLE></CENTER><BR><A name=6><I><FONT size=+2>ECP 
        Reverse Data Cycle</FONT></I></A> 
        <HR>
        <BR>
        <CENTER>
        <TABLE border=0>
          <TBODY>
          <TR>
            <TD><IMG alt="Enhanced Capabilities Port Reverse Data Cycle" 
              src="Interfacing the Extended Capabilities Port.files/ecprdata.gif" 
              border=0> <BR>
              <CENTER><FONT size=-1>Figure 3. Enhanced Capabilities Port Reverse 
              Data Cycle.</FONT></CENTER></TD>
            <TD>
              <UL><B>1. Host sets nReverseRequest Low to request a reverse 
                channel.</B><BR>2. Peripheral acknowledges reverse channel 
                request via asserting nAckReverse low.<BR><B>3. Data is placed 
                on data lines by Peripheral.</B><BR>4. Data cycle is then 
                selected by Peripheral via PeriphAck going high.<BR><B>5. Valid 
                data is indicated by the Peripheral setting PeriphClk 
                low.</B><BR>6. Host sends its acknowledgment of valid data via 
                HostAck going high.<BR><B>7. Device/Peripheral sets PeriphClk 
                high. +ve edge used to shift data into the Host.</B><BR>8. Host 
                sends it's acknowledgment of the byte by de-asserting HostAck 
                low. </UL></TD></TR></TBODY></TABLE></CENTER><BR><A name=7><I><FONT 
        size=+2>ECP Reverse Command Cycle</FONT></I></A> 
        <HR>
        <BR>
        <CENTER>
        <TABLE border=0>
          <TBODY>
          <TR>
            <TD><IMG alt="Enhanced Capabilities Port Reverse Command Cycle" 
              src="Interfacing the Extended Capabilities Port.files/ecprcomm.gif" 
              border=0> <BR>
              <CENTER><FONT size=-1>Figure 4. Enhanced Capabilities Port Reverse 
              Command Cycle.</FONT></CENTER></TD>
            <TD><B>1. Host sets nReverseRequest Low to request a reverse 
              channel.</B><BR>2. Peripheral acknowledges reverse channel request 
              via asserting nAckReverse low.<BR><B>3. Data is placed on data 
              lines by Peripheral.</B><BR>4. Command cycle is then selected by 
              Peripheral via PeriphAck going low.<BR><B>5. Valid data is 
              indicated by the Peripheral setting PeriphClk low.</B><BR>6. Host 
              sends its acknowledgment of valid data via HostAck going 
              high.<BR><B>7. Device/Peripheral sets PeriphClk high. +ve edge 
              used to shift data into the Host.</B><BR>8. Host sends it's 
              acknowledgment of the byte by de-asserting HostAck low. 
          </TD></TR></TBODY></TABLE></CENTER><BR><A name=13><I><FONT size=+2>ECP 
        Handshake vs SPP Handshake</FONT></I></A> 
        <HR>

        <P>If we look back at the SPP Handshake you will realize it only has 5 
        steps, <BR><BR>
        <UL><I>1. Write the byte to the Data Port.</I> <BR><I>2. Check to see 
          is the printer is busy. If the printer is busy, it will not accept any 
          data, thus any data which is written will be lost.</I> <BR><I>3. Take 
          the Strobe (Pin 1) low. This tells the printer that there is the 
          correct data on the data lines. (Pins 2-9)</I> <BR><I>4. Put the 
          strobe high again after waiting approximately 5 microseconds after 
          putting the strobe low. (Step 3)</I> <BR><I>5. Check for Ack from 
          Peripheral.</I> </UL>
        <P></P>
        <P>and that the ECP handshake has many more steps. This would suggest 
        that ECP would be slower that SPP. However this is not the case as all 
        of these steps above are controlled by the hardware on your I/O control. 
        If this handshake was implemented via software control then it would be 
        a lot slower that it's SPP counterpart. </P></UL><A name=8><I><FONT 
      size=+2>RLE - Run Length Encoding</FONT></I></A> 
      <HR>

      <UL>
        <P>As briefly discussed earlier, the ECP Protocol includes a Simple 
        Compression Scheme called Run Length Encoding. It can support a maximum 
        compression ratio of 64:1 and works by sending repetitive single bytes 
        as a run count and one copy of the byte. The run count determines how 
        many times the following byte is to be repeated. </P>
        <P>For example, if a string of 25 'A's were to be sent, then a run count 
        byte equal to 24 would be sent first, followed by the byte 'A'. The 
        receiving peripheral on receipt of the Run Length Count, would expand 
        (Repeat) the next byte a number of times determined via the run count. 
        </P>
        <P>The Run Length Byte has to be distinguished from other bytes in the 
        Data Path. It is sent as a Command to the ECP's Address FIFO Port. Bytes 
        sent to this register can be of two things, a Run Length Count or an 
        Address. These are distinguished by the MSB, Bit 7. If Bit 7 is Set (1), 
        then the other 7 bits, bits 0 to 6 is a channel address. If Bit 7 is 
        Reset (0), then the lower 7 bits is a run length count. By using the 
        MSB, this limits channel Addresses and Run Length Counts to 7 Bits (0 - 
        127). </P></UL><A name=9><I><FONT size=+2>ECP Software 
      Registers</FONT></I></A> 
      <HR>

      <UL>
        <P>The table below shows the registers of the Extended Capabilities 
        Port. The first 3 registers are exactly the same than with the Standard 
        Parallel Port registers. Note should be taken, however, of the Enable 
        Bi-Directional Port bit (bit 5 of the Control Port.) This bit reflects 
        the direction that the ECP port is currently in, and will effect the 
        FIFO燜ull and FIFO燛mpty bits of the ECR Register, which will be explained 
        later. </P>
        <P>
        <CENTER>
        <TABLE width="70%" border=1>
          <TBODY>
          <TR>
            <TD>
              <CENTER><B>Address</B></CENTER></TD>
            <TD>
              <CENTER><B>Port Name</B></CENTER></TD>
            <TD>
              <CENTER><B>Read/Write</B></CENTER></TD></TR>
          <TR>
            <TD vAlign=top rowSpan=2>
              <CENTER>Base + 0</CENTER></TD>
            <TD>
              <CENTER>Data Port (SPP)</CENTER></TD>
            <TD>
              <CENTER>Write</CENTER></TD></TR>
          <TR>
            <TD>
              <CENTER>ECP Address FIFO (ECP MODE)</CENTER></TD>
            <TD>
              <CENTER>Read/Write</CENTER></TD></TR>
          <TR>
            <TD>
              <CENTER>Base + 1</CENTER></TD>
            <TD>
              <CENTER>Status Port (All Modes)</CENTER></TD>
            <TD>
              <CENTER>Read/Write</CENTER></TD></TR>
          <TR>
            <TD>
              <CENTER>Base + 2</CENTER></TD>
            <TD>
              <CENTER>Control Port (All Modes)</CENTER></TD>
            <TD>
              <CENTER>Read/Write</CENTER></TD></TR>
          <TR>
            <TD vAlign=top rowSpan=4>
              <CENTER>Base + 400h</CENTER></TD>
            <TD>
              <CENTER>Data FIFO (Parallel Port FIFO Mode)</CENTER></TD>
            <TD>
              <CENTER>Read/Write</CENTER></TD></TR>
          <TR>
            <TD>
              <CENTER>Data FIFO (ECP Mode)</CENTER></TD>
            <TD>
              <CENTER>Read/Write</CENTER></TD></TR>
          <TR>
            <TD>
              <CENTER>Test FIFO (Test Mode)</CENTER></TD>
            <TD>
              <CENTER>Read/Write</CENTER></TD></TR>
          <TR>
            <TD>
              <CENTER>Configuration Register A (Configuration Mode)</CENTER></TD>
            <TD>
              <CENTER>Read/Write</CENTER></TD></TR>
          <TR>
            <TD>
              <CENTER>Base + 401h</CENTER></TD>
            <TD>
              <CENTER>Configuration Register B (Configuration Mode)</CENTER></TD>
            <TD>
              <CENTER>Read/Write</CENTER></TD></TR>
          <TR>
            <TD>
              <CENTER>Base + 402h</CENTER></TD>
            <TD>
              <CENTER>Extended Control Register (Used by all modes)</CENTER></TD>
            <TD>
              <CENTER>Read/Write</CENTER></TD></TR></TBODY></TABLE><FONT size=-1>Table 
        2 : ECP Registers</FONT></CENTER>
        <P></P><A name=10><I><FONT size=+2>ECP's Extended Control Register 
        (ECR)</FONT></I></A> 
        <HR>

        <UL>
          <P>The most important register with a Extended Capabilities Parallel 
          Port is the Extended Control Register (ECR) thus we will target it's 
          operation first. This register sets up the mode in which the ECP will 
          run, plus gives status of the ECP's FIFO among other things. You will 
          find the contents of this register below, in more detail. </P>
          <P>
          <CENTER>
          <TABLE width="65%" border=1>
            <TBODY>
            <TR>
              <TD width="10%">
                <CENTER><B>Bit</B></CENTER></TD>
              <TD colSpan=2>
                <CENTER><B>Function</B></CENTER></TD></TR>
            <TR>
              <TD vAlign=top rowSpan=9>
                <CENTER>7:5</CENTER></TD>
              <TD colSpan=2><I>Selects Current Mode of Operation</I></TD></TR>
            <TR>
              <TD width="10%">
                <CENTER>000</CENTER></TD>
              <TD>Standard Mode</TD></TR>
            <TR>
              <TD>
                <CENTER>001</CENTER></TD>
              <TD>Byte Mode</TD></TR>
            <TR>
              <TD>
                <CENTER>010</CENTER></TD>
              <TD>Parallel Port FIFO Mode</TD></TR>
            <TR>
              <TD>
                <CENTER>011</CENTER></TD>
              <TD>ECP FIFO Mode</TD></TR>
            <TR>
              <TD>
                <CENTER>100</CENTER></TD>
              <TD>EPP Mode</TD></TR>
            <TR>
              <TD>
                <CENTER>101</CENTER></TD>
              <TD>Reserved</TD></TR>
            <TR>
              <TD>
                <CENTER>110</CENTER></TD>
              <TD>FIFO Test Mode</TD></TR>
            <TR>
              <TD>
                <CENTER>111</CENTER></TD>
              <TD>Configuration Mode</TD></TR>
            <TR>
              <TD>
                <CENTER>4</CENTER></TD>
              <TD colSpan=2>ECP Interrupt Bit</TD></TR>
            <TR>
              <TD>
                <CENTER>3</CENTER></TD>
              <TD colSpan=2>DMA Enable Bit</TD></TR>
            <TR>
              <TD>
                <CENTER>2</CENTER></TD>
              <TD colSpan=2>ECP Service Bit</TD></TR>
            <TR>
              <TD>
                <CENTER>1</CENTER></TD>
              <TD colSpan=2>FIFO Full</TD></TR>
            <TR>
              <TD>
                <CENTER>0</CENTER></TD>
              <TD colSpan=2>FIFO Empty</TD></TR></TBODY></TABLE><FONT size=-1>Table 
          3 ECR - Extended Control Register</FONT></CENTER>
          <P></P>
          <P>The three MSB of the Extended Control Register selects the mode of 
          operation. There are 7 possible modes of operation, but not all ports 
          will support all modes. The EPP爉ode is one such example, not being 
          available on some ports. Below is a table of Modes of Operation. </P>
          <P>
          <CENTER>
          <TABLE width="90%">
            <TBODY>
            <TR>
              <TD width="25%" colSpan=2>
                <CENTER>
                <HR>
                <B>Modes of Operation</B>
                <HR>
                </CENTER></TD></TR>
            <TR>
              <TD vAlign=top>Standard Mode</TD>
              <TD>Selecting this mode will cause the ECP port to behave as a 
                Standard Parallel Port, without Bi-directional 
            functionality.</TD></TR>
            <TR>
              <TD vAlign=top>Byte Mode / PS/2 Mode</TD>
              <TD>Behaves as a SPP in Bi-directional (Reverse) mode.</TD></TR>
            <TR>
              <TD vAlign=top>Parallel Port FIFO Mode</TD>