<TD>In this mode, any data written to the Data FIFO will be sent 
                to the peripheral using the SPP Handshake. The hardware will 
                generate the handshaking required. Useful with non-ECP devices 
                such as Printers. You can have some of the features of ECP like 
                FIFO buffers and hardware generation of handshaking but爓ith the 
                existing SPP爃andshake instead of the ECP燞andshake.</TD></TR>
            <TR>
              <TD vAlign=top>ECP FIFO Mode</TD>
              <TD>Standard Mode for ECP Use. This mode uses the ECP Handshake, 
                already described.</TD></TR>
            <TR>
              <TD vAlign=top>EPP Mode<I>/Reserved</I></TD>
              <TD>On some chipsets, this mode will enable EPP to be used. 
                While on others, this mode is still reserved.</TD></TR>
            <TR>
              <TD vAlign=top>Reserved</TD>
              <TD>Currently Reserved</TD></TR>
            <TR>
              <TD vAlign=top>FIFO Test Mode</TD>
              <TD>While in this mode, any data written to the Test FIFO 
                Register will be placed into the FIFO and any data read from the 
                Test FIFO register will be read from the FIFO燽uffer. The FIFO 
                Full/Empty Status Bits will reflect their true value, thus FIFO 
                depth, among other things can be determined in this mode. </TD></TR>
            <TR>
              <TD vAlign=top>Configuration Mode</TD>
              <TD>In this mode, the two configuration registers, cnfgA &amp; 
                cnfgB become available at their designated Register 
            Addresses.</TD></TR>
            <TR>
              <TD colSpan=2>
                <HR>
              </TD></TR></TBODY></TABLE></CENTER>
          <P></P>
          <P>As outlined above, when the port is set to operate in Standard 
          Mode, it will behave just like a Standard Parallel Port (SPP) with no 
          bi-directional data transfer. If you require bi-directional transfer, 
          then set the mode to Byte Mode. The Parallel Port FIFO mode and ECP 
          FIFO mode both use hardware to generate the necessary handshaking 
          signals. The only difference between each mode is that The Parallel 
          Port FIFO Mode uses SPP handshaking, thus can be used with your SPP 
          printer. ECP FIFO mode uses ECP handshaking. </P>
          <P>The FIFO test mode can be used to test the capacity of the FIFO 
          Buffers as well as to make sure they function correctly. When in FIFO 
          test mode, any byte which is written to the TEST FIFO (Base + 400h) is 
          placed into the FIFO buffer and any byte which is read from this 
          register is taken from the FIFO Buffer. You can use this along with 
          the FIFO Full and FIFO Empty bits of the Extended Control Register to 
          determine the capacity of the FIFO Buffer. This should normally be 
          about 16 Bytes deep. </P>
          <P>The other Bits of the ECR also play an important role in the 
          operation of the ECP燩ort. The ECP營nterrupt Bit, (Bit 4) enables the 
          use of Interrupts, while the DMA Enable Bit (Bit 3) enables the use of 
          Direct Memory Access. The ECP燬ervice Bit (Bit 2) shows if an interrupt 
          request has been initiated. If so, this bit will be set. Resetting 
          this bit is different with different chips. Some require you to Reset 
          the Bit, E.g. Write a Zero to it. Others will reset once the Register 
          has been read. </P>
          <P>The FIFO Full (Bit 1) and FIFO Empty (Bit 0) show the status of the 
          FIFO Buffer. These bits are direction dependent, thus note should be 
          taken of the Control Register's Bit 5. If bit 0 (FIFO Empty) is set, 
          then the FIFO buffer is completely empty. If Bit 1 is set then the 
          FIFO buffer is Full. Thus, if neither bit 0 or 1 is set, then there is 
          data in FIFO, but is not yet full. These bits can be used in FIFO Test 
          Mode, to determine the capacity of the FIFO Buffer. </P></UL><BR><A 
        name=11><I><FONT size=+2>ECP's Configuration Register A 
        (cnfgA)</FONT></I></A> 
        <HR>

        <UL>
          <P>Configuration Register A is one of two configuration registers 
          which the ECP Port has. These Configuration Registers are only 
          accessible when the ECP Port is in Configuration Mode. (See Extended 
          Control Register) CnfgA can be accessed at Base + 400h. </P>
          <P>
          <CENTER>
          <TABLE width="80%" border=1>
            <TBODY>
            <TR>
              <TD width="10%">
                <CENTER><B>Bit</B></CENTER></TD>
              <TD colSpan=2>
                <CENTER><B>Function</B></CENTER></TD></TR>
            <TR>
              <TD vAlign=top rowSpan=2>
                <CENTER>7</CENTER></TD>
              <TD width="10%">
                <CENTER>1</CENTER></TD>
              <TD>Interrupts are level triggered</TD></TR>
            <TR>
              <TD>
                <CENTER>0</CENTER></TD>
              <TD>Interrupts are edge triggered (Pulses)</TD></TR>
            <TR>
              <TD vAlign=top rowSpan=4>
                <CENTER>6:4</CENTER></TD>
              <TD>
                <CENTER>00h</CENTER></TD>
              <TD>Accepts Max. 16 Bit wide words</TD></TR>
            <TR>
              <TD>
                <CENTER>01h</CENTER></TD>
              <TD>Accepts Max. 8 Bit wide words</TD></TR>
            <TR>
              <TD>
                <CENTER>02h</CENTER></TD>
              <TD>Accepts Max. 32 Bit wide words</TD></TR>
            <TR>
              <TD>
                <CENTER>03h:07h</CENTER></TD>
              <TD>Reserved for future expansion</TD></TR>
            <TR>
              <TD>
                <CENTER>3</CENTER></TD>
              <TD colSpan=2>Reserved</TD></TR>
            <TR>
              <TD vAlign=top rowSpan=3>
                <CENTER>2</CENTER></TD>
              <TD colSpan=2><I>Host Recovery : Pipeline/Transmitter Byte 
                included in FIFO?</I></TD></TR>
            <TR>
              <TD>
                <CENTER>0</CENTER></TD>
              <TD>In forward direction, the 1 byte in the transmitter pipeline 
                doesn't affect FIFO Full.</TD></TR>
            <TR>
              <TD>
                <CENTER>1</CENTER></TD>
              <TD>In forward direction, the 1 byte in the transmitter pipeline 
                is include as part of FIFO Full.</TD></TR>
            <TR>
              <TD vAlign=top rowSpan=5>
                <CENTER>1:0</CENTER></TD>
              <TD colSpan=2><I>Host Recovery : Unsent byte(s) left in 
              FIFO</I></TD></TR>
            <TR>
              <TD>
                <CENTER>00</CENTER></TD>
              <TD>Complete Pword</TD></TR>
            <TR>
              <TD>
                <CENTER>01</CENTER></TD>
              <TD>1 Valid Byte</TD></TR>
            <TR>
              <TD>
                <CENTER>10</CENTER></TD>
              <TD>2 Valid Bytes</TD></TR>
            <TR>
              <TD>
                <CENTER>11</CENTER></TD>
              <TD>3 Valid Bytes</TD></TR></TBODY></TABLE><FONT size=-1>Table 4 - 
          Configuration Register A</FONT></CENTER>
          <P></P>
          <P>Configuration Register A can be read to find out a little more 
          about the ECP Port. The MSB, shows if the card generates level 
          interrupts or edge triggered interrupts. This will depend upon the 
          type of bus your card is using. Bits 4 to 6, show the buses width 
          within the card. Some cards only have a 8 bit data path, while others 
          may have a 32 or 16 bit width. To get maximum efficiency from your 
          card, the software can read the status of these bits to determine the 
          Maximum Word Size to output to the port. </P>
          <P>The 3 LSB's are used for Host Recovery. In order to recover from an 
          error, the software must know how many bytes were sent, by determining 
          if there are any bytes left in the FIFO. Some implementations may 
          include the byte sitting in the transmitter register, waiting to be 
          sent as part of the FIFO's Full Status, while others may not. Bit 2 
          determines weather or not this is the case. </P>
          <P>The other problem is that the Parallel Ports output is only 8 bits 
          wide, and that you many be using 16 bit or 32 bit I/O營nstructions. If 
          this is the case, then part of your Port Word (Word you sent to port) 
          may be sent. Therefore Bits 0 and 1 give an indication of the number 
          of valid bytes still left in the FIFO, so that you can retransmit 
          these. </P></UL><A name=12><I><FONT size=+2>ECP's Configuration Register 
        B (cnfgB)</FONT></I></A> 
        <HR>

        <UL>
          <P>Configuration Register B, like Configuration Register A is only 
          available when the ECP Port is in Configuration Mode. When in this 
          mode, cnfgB resides at Base + 401h. Below is the make-up of the cnfgB 
          Register. </P>
          <P>
          <CENTER>
          <TABLE width="65%" border=1>
            <TBODY>
            <TR>
              <TD width="10%">
                <CENTER><B>Bit(s)</B></CENTER></TD>
              <TD colSpan=2>
                <CENTER><B>Function</B></CENTER></TD></TR>
            <TR>
              <TD vAlign=top rowSpan=2>
                <CENTER>7</CENTER></TD>
              <TD width="10%">
                <CENTER>1</CENTER></TD>
              <TD>Compress outgoing Data Using RLE</TD></TR>
            <TR>
              <TD>
                <CENTER>0</CENTER></TD>
              <TD>Do Not compress Data</TD></TR>
            <TR>
              <TD>
                <CENTER>6</CENTER></TD>
              <TD colSpan=2>Interrupt Status - Shows the Current Status of the 
                IRQ Pin</TD></TR>
            <TR>
              <TD vAlign=top rowSpan=9>
                <CENTER>5:3</CENTER></TD>
              <TD colSpan=2><I>Selects or Displays Status of Interrupt Request 
                Line.</I></TD></TR>
            <TR>
              <TD>
                <CENTER>000</CENTER></TD>
              <TD>Interrupt Selected Via Jumper</TD></TR>
            <TR>
              <TD>
                <CENTER>001</CENTER></TD>
              <TD>IRQ 7</TD></TR>
            <TR>
              <TD>
                <CENTER>010</CENTER></TD>
              <TD>IRQ 9</TD></TR>
            <TR>
              <TD>
                <CENTER>011</CENTER></TD>
              <TD>IRQ 10</TD></TR>
            <TR>
              <TD>
                <CENTER>100</CENTER></TD>
              <TD>IRQ 11</TD></TR>
            <TR>
              <TD>
                <CENTER>101</CENTER></TD>
              <TD>IRQ 14</TD></TR>
            <TR>
              <TD>
                <CENTER>110</CENTER></TD>
              <TD>IRQ 15</TD></TR>
            <TR>
              <TD>
                <CENTER>111</CENTER></TD>
              <TD>IRQ 5</TD></TR>
            <TR>
              <TD vAlign=top rowSpan=9>
                <CENTER>2:0</CENTER></TD>
              <TD colSpan=2><I>Selects or Displays Status of the DMA Channel 
                the Printer Card Uses</I></TD></TR>
            <TR>
              <TD>
                <CENTER>000</CENTER></TD>
              <TD>Uses a Jumpered 8 Bit DMA Channel</TD></TR>
            <TR>
              <TD>
                <CENTER>001</CENTER></TD>
              <TD>DMA Channel 1</TD></TR>
            <TR>
              <TD>
                <CENTER>010</CENTER></TD>
              <TD>DMA Channel 2</TD></TR>
            <TR>
              <TD>
                <CENTER>011</CENTER></TD>
              <TD>DMA Channel 3</TD></TR>
            <TR>
              <TD>
                <CENTER>100</CENTER></TD>
              <TD>Uses a Jumpered 16 Bit DMA Channel</TD></TR>
            <TR>
              <TD>
                <CENTER>101</CENTER></TD>
              <TD>DMA Channel 5</TD></TR>
            <TR>
              <TD>
                <CENTER>110</CENTER></TD>
              <TD>DMA Channel 6</TD></TR>
            <TR>
              <TD>
                <CENTER>111</CENTER></TD>
              <TD>DMA Channel 7</TD></TR></TBODY></TABLE><FONT size=-1>Table 5 - 
          Configuration B Register</FONT></CENTER>
          <P></P>
          <P>The Configuration Register B (cnfgB) can be a combination of 
          read/write access. Some ports may be software configurable, where you 
          can set the IRQ and DMA resources from the register. Others may be set 
          via BIOS or by using jumpers on the Card, thus are read only. </P>
          <P>Bit 7 of the cnfgB Register selects whether to compress outgoing 
          data using RLE (Run Length Encoding.) When Set, the host will compress 
          the data before sending. When reset, data will be sent to the 
          peripheral raw (Uncompressed). Bit 6 returns the status of the IRQ 
          pin. This can be used to diagnose conflicts as it will not only 
          reflect the status of the Parallel Ports IRQ, but and other device 
          using this IRQ. </P>
          <P>Bits 5 to 3 give status of about the Port's IRQ assignment. 
          Likewise for bits 2 to 0 which give status of DMA Channel assignment. 
          As mentioned above these fields may be read/write. The disappearing 
          species of Parallel Cards which have Jumpers may simply show it's 
          resources as "Jumpered" or it may show the correct Line Numbers. 
          However these of course will be read only. 
</P></UL></UL></TD></TR></TBODY></TABLE><FONT size=2>Copyright 1997-2005 <A 
href="http://www.beyondlogic.org/about.htm">Craig Peacock</A> - 15th June 
2005.</FONT> <BR><BR></CENTER></FONT></BODY></HTML>