(~(cpu_0_data_master_requests_payload_buffer_s1 & ~cpu_0_data_master_waitrequest & cpu_0_data_master_write));

  //dbs counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_data_master_dbs_address <= 0;
      else if (dbs_count_enable)
          cpu_0_data_master_dbs_address <= next_dbs_address;
    end



  // synthesis attribute cpu_0_data_master_arbitrator auto_dissolve FALSE

endmodule


module cpu_0_instruction_master_arbitrator (
                                             // inputs:
                                              cfi_flash_0_s1_wait_counter_eq_0,
                                              cfi_flash_0_s1_wait_counter_eq_1,
                                              cfi_flash_1_s1_wait_counter_eq_0,
                                              cfi_flash_1_s1_wait_counter_eq_1,
                                              clk,
                                              cpu_0_instruction_master_address,
                                              cpu_0_instruction_master_granted_cfi_flash_0_s1,
                                              cpu_0_instruction_master_granted_cfi_flash_1_s1,
                                              cpu_0_instruction_master_granted_data_RAM_s1,
                                              cpu_0_instruction_master_granted_firmware_ROM_s1,
                                              cpu_0_instruction_master_granted_payload_buffer_s1,
                                              cpu_0_instruction_master_qualified_request_cfi_flash_0_s1,
                                              cpu_0_instruction_master_qualified_request_cfi_flash_1_s1,
                                              cpu_0_instruction_master_qualified_request_data_RAM_s1,
                                              cpu_0_instruction_master_qualified_request_firmware_ROM_s1,
                                              cpu_0_instruction_master_qualified_request_payload_buffer_s1,
                                              cpu_0_instruction_master_read,
                                              cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1,
                                              cpu_0_instruction_master_read_data_valid_cfi_flash_1_s1,
                                              cpu_0_instruction_master_read_data_valid_data_RAM_s1,
                                              cpu_0_instruction_master_read_data_valid_firmware_ROM_s1,
                                              cpu_0_instruction_master_read_data_valid_payload_buffer_s1,
                                              cpu_0_instruction_master_requests_cfi_flash_0_s1,
                                              cpu_0_instruction_master_requests_cfi_flash_1_s1,
                                              cpu_0_instruction_master_requests_data_RAM_s1,
                                              cpu_0_instruction_master_requests_firmware_ROM_s1,
                                              cpu_0_instruction_master_requests_payload_buffer_s1,
                                              d1_data_RAM_s1_end_xfer,
                                              d1_firmware_ROM_s1_end_xfer,
                                              d1_payload_buffer_s1_end_xfer,
                                              d1_tri_state_bridge_0_avalon_slave_end_xfer,
                                              data_RAM_s1_readdata_from_sa,
                                              firmware_ROM_s1_readdata_from_sa,
                                              incoming_tri_state_bridge_0_data,
                                              payload_buffer_s1_readdata_from_sa,
                                              reset_n,

                                             // outputs:
                                              cpu_0_instruction_master_address_to_slave,
                                              cpu_0_instruction_master_dbs_address,
                                              cpu_0_instruction_master_latency_counter,
                                              cpu_0_instruction_master_readdata,
                                              cpu_0_instruction_master_readdatavalid,
                                              cpu_0_instruction_master_waitrequest
                                           );

  output  [ 22: 0] cpu_0_instruction_master_address_to_slave;
  output  [  1: 0] cpu_0_instruction_master_dbs_address;
  output  [  1: 0] cpu_0_instruction_master_latency_counter;
  output  [ 31: 0] cpu_0_instruction_master_readdata;
  output           cpu_0_instruction_master_readdatavalid;
  output           cpu_0_instruction_master_waitrequest;
  input            cfi_flash_0_s1_wait_counter_eq_0;
  input            cfi_flash_0_s1_wait_counter_eq_1;
  input            cfi_flash_1_s1_wait_counter_eq_0;
  input            cfi_flash_1_s1_wait_counter_eq_1;
  input            clk;
  input   [ 22: 0] cpu_0_instruction_master_address;
  input            cpu_0_instruction_master_granted_cfi_flash_0_s1;
  input            cpu_0_instruction_master_granted_cfi_flash_1_s1;
  input            cpu_0_instruction_master_granted_data_RAM_s1;
  input            cpu_0_instruction_master_granted_firmware_ROM_s1;
  input            cpu_0_instruction_master_granted_payload_buffer_s1;
  input            cpu_0_instruction_master_qualified_request_cfi_flash_0_s1;
  input            cpu_0_instruction_master_qualified_request_cfi_flash_1_s1;
  input            cpu_0_instruction_master_qualified_request_data_RAM_s1;
  input            cpu_0_instruction_master_qualified_request_firmware_ROM_s1;
  input            cpu_0_instruction_master_qualified_request_payload_buffer_s1;
  input            cpu_0_instruction_master_read;
  input            cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1;
  input            cpu_0_instruction_master_read_data_valid_cfi_flash_1_s1;
  input            cpu_0_instruction_master_read_data_valid_data_RAM_s1;
  input            cpu_0_instruction_master_read_data_valid_firmware_ROM_s1;
  input            cpu_0_instruction_master_read_data_valid_payload_buffer_s1;
  input            cpu_0_instruction_master_requests_cfi_flash_0_s1;
  input            cpu_0_instruction_master_requests_cfi_flash_1_s1;
  input            cpu_0_instruction_master_requests_data_RAM_s1;
  input            cpu_0_instruction_master_requests_firmware_ROM_s1;
  input            cpu_0_instruction_master_requests_payload_buffer_s1;
  input            d1_data_RAM_s1_end_xfer;
  input            d1_firmware_ROM_s1_end_xfer;
  input            d1_payload_buffer_s1_end_xfer;
  input            d1_tri_state_bridge_0_avalon_slave_end_xfer;
  input   [ 31: 0] data_RAM_s1_readdata_from_sa;
  input   [ 31: 0] firmware_ROM_s1_readdata_from_sa;
  input   [ 15: 0] incoming_tri_state_bridge_0_data;
  input   [ 15: 0] payload_buffer_s1_readdata_from_sa;
  input            reset_n;

  reg              active_and_waiting_last_time;
  reg     [ 22: 0] cpu_0_instruction_master_address_last_time;
  wire    [ 22: 0] cpu_0_instruction_master_address_to_slave;
  reg     [  1: 0] cpu_0_instruction_master_dbs_address;
  wire    [  1: 0] cpu_0_instruction_master_dbs_increment;
  reg     [  1: 0] cpu_0_instruction_master_dbs_rdv_counter;
  wire    [  1: 0] cpu_0_instruction_master_dbs_rdv_counter_inc;
  wire             cpu_0_instruction_master_is_granted_some_slave;
  reg     [  1: 0] cpu_0_instruction_master_latency_counter;
  wire    [  1: 0] cpu_0_instruction_master_next_dbs_rdv_counter;
  reg              cpu_0_instruction_master_read_but_no_slave_selected;
  reg              cpu_0_instruction_master_read_last_time;
  wire    [ 31: 0] cpu_0_instruction_master_readdata;
  wire             cpu_0_instruction_master_readdatavalid;
  wire             cpu_0_instruction_master_run;
  wire             cpu_0_instruction_master_waitrequest;
  wire             dbs_count_enable;
  wire             dbs_counter_overflow;
  reg     [ 15: 0] dbs_latent_16_reg_segment_0;
  wire             dbs_rdv_count_enable;
  wire             dbs_rdv_counter_overflow;
  wire             dummy_sink;
  wire    [  1: 0] latency_load_value;
  wire    [  1: 0] next_dbs_address;
  wire    [  1: 0] p1_cpu_0_instruction_master_latency_counter;
  wire    [ 15: 0] p1_dbs_latent_16_reg_segment_0;
  wire             pre_dbs_count_enable;
  wire             pre_flush_cpu_0_instruction_master_readdatavalid;
  wire             r_0;
  wire             r_1;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (cpu_0_instruction_master_qualified_request_data_RAM_s1 | ~cpu_0_instruction_master_requests_data_RAM_s1) & (cpu_0_instruction_master_granted_data_RAM_s1 | ~cpu_0_instruction_master_qualified_request_data_RAM_s1) & ((~cpu_0_instruction_master_qualified_request_data_RAM_s1 | ~cpu_0_instruction_master_read | (1 & cpu_0_instruction_master_read))) & 1 & (cpu_0_instruction_master_qualified_request_firmware_ROM_s1 | ~cpu_0_instruction_master_requests_firmware_ROM_s1) & (cpu_0_instruction_master_granted_firmware_ROM_s1 | ~cpu_0_instruction_master_qualified_request_firmware_ROM_s1) & ((~cpu_0_instruction_master_qualified_request_firmware_ROM_s1 | ~cpu_0_instruction_master_read | (1 & cpu_0_instruction_master_read))) & 1 & (cpu_0_instruction_master_qualified_request_payload_buffer_s1 | ~cpu_0_instruction_master_requests_payload_buffer_s1);

  //cascaded wait assignment, which is an e_assign
  assign cpu_0_instruction_master_run = r_0 & r_1;

  //r_1 master_run cascaded wait assignment, which is an e_assign
  assign r_1 = (cpu_0_instruction_master_granted_payload_buffer_s1 | ~cpu_0_instruction_master_qualified_request_payload_buffer_s1) & ((~cpu_0_instruction_master_qualified_request_payload_buffer_s1 | ~cpu_0_instruction_master_read | (1 & (cpu_0_instruction_master_dbs_address[1]) & cpu_0_instruction_master_read))) & 1 & (cpu_0_instruction_master_qualified_request_cfi_flash_0_s1 | ~cpu_0_instruction_master_requests_cfi_flash_0_s1) & (cpu_0_instruction_master_qualified_request_cfi_flash_1_s1 | ~cpu_0_instruction_master_requests_cfi_flash_1_s1) & (cpu_0_instruction_master_granted_cfi_flash_0_s1 | ~cpu_0_instruction_master_qualified_request_cfi_flash_0_s1) & (cpu_0_instruction_master_granted_cfi_flash_1_s1 | ~cpu_0_instruction_master_qualified_request_cfi_flash_1_s1) & ((~cpu_0_instruction_master_qualified_request_cfi_flash_0_s1 | ~cpu_0_instruction_master_read | (1 & ((cfi_flash_0_s1_wait_counter_eq_0 & ~d1_tri_state_bridge_0_avalon_slave_end_xfer)) & (cpu_0_instruction_master_dbs_address[1]) & cpu_0_instruction_master_read))) & ((~cpu_0_instruction_master_qualified_request_cfi_flash_1_s1 | ~cpu_0_instruction_master_read | (1 & ((cfi_flash_1_s1_wait_counter_eq_0 & ~d1_tri_state_bridge_0_avalon_slave_end_xfer)) & (cpu_0_instruction_master_dbs_address[1]) & cpu_0_instruction_master_read)));

  //optimize select-logic by passing only those address bits which matter.
  assign cpu_0_instruction_master_address_to_slave = cpu_0_instruction_master_address[22 : 0];

  //dummy sink, which is an e_mux
  assign dummy_sink = cpu_0_instruction_master_address_to_slave |
    cpu_0_instruction_master_requests_data_RAM_s1 |
    cpu_0_instruction_master_qualified_request_data_RAM_s1 |
    d1_data_RAM_s1_end_xfer |
    cpu_0_instruction_master_address_to_slave |
    cpu_0_instruction_master_requests_firmware_ROM_s1 |
    cpu_0_instruction_master_qualified_request_firmware_ROM_s1 |
    d1_firmware_ROM_s1_end_xfer |
    cpu_0_instruction_master_address_to_slave |
    cpu_0_instruction_master_requests_payload_buffer_s1 |
    cpu_0_instruction_master_qualified_request_payload_buffer_s1 |
    d1_payload_buffer_s1_end_xfer |
    cpu_0_instruction_master_address_to_slave |
    cpu_0_instruction_master_requests_cfi_flash_0_s1 |
    cpu_0_instruction_master_qualified_request_cfi_flash_0_s1 |
    cpu_0_instruction_master_address_to_slave |
    cpu_0_instruction_master_requests_cfi_flash_1_s1 |
    cpu_0_instruction_master_qualified_request_cfi_flash_1_s1 |
    d1_tri_state_bridge_0_avalon_slave_end_xfer |
    cfi_flash_0_s1_wait_counter_eq_0 |
    cfi_flash_1_s1_wait_counter_eq_0;

  //cpu_0_instruction_master_read_but_no_slave_selected assignment, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_instruction_master_read_but_no_slave_selected <= 0;
      else if (1)
          cpu_0_instruction_master_read_but_no_slave_selected <= cpu_0_instruction_master_read & cpu_0_instruction_master_run & ~cpu_0_instruction_master_is_granted_some_slave;
    end


  //some slave is getting selected, which is an e_mux
  assign cpu_0_instruction_master_is_granted_some_slave = cpu_0_instruction_master_granted_data_RAM_s1 |
    cpu_0_instruction_master_granted_firmware_ROM_s1 |
    cpu_0_instruction_master_granted_payload_buffer_s1 |
    cpu_0_instruction_master_granted_cfi_flash_0_s1 |
    cpu_0_instruction_master_granted_cfi_flash_1_s1;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_cpu_0_instruction_master_readdatavalid = cpu_0_instruction_master_read_data_valid_data_RAM_s1 |
    cpu_0_instruction_master_read_data_valid_firmware_ROM_s1 |
    (cpu_0_instruction_master_read_data_valid_payload_buffer_s1 & dbs_rdv_counter_overflow) |
    (cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 & dbs_rdv_counter_overflow) |
    (cpu_0_instruction_master_read_data_valid_cfi_flash_1_s1 & dbs_rdv_counter_overflow);

  //latent slave read data valid which is not flushed, which is an e_mux
  assign cpu_0_instruction_master_readdatavalid = cpu_0_instruction_master_read_but_no_slave_selected |
    pre_flush_cpu_0_instruction_master_readdatavalid |
    cpu_0_instruction_master_read_but_no_slave_selected |
    pre_flush_cpu_0_instruction_master_readdatavalid |
    cpu_0_instruction_master_read_but_no_slave_selected |
    pre_flush_cpu_0_instruction_master_readdatavalid |
    cpu_0_instruction_master_read_but_no_slave_selected |
    pre_flush_cpu_0_instruction_master_readdatavalid |
    cpu_0_instruction_master_read_but_no_slave_selected |
    pre_flush_cpu_0_instruction_master_readdatavalid;

  //cpu_0/instruction_master readdata mux, which is an e_mux
  assign cpu_0_instruction_master_readdata = ({32 {~cpu_0_instruction_master_read_data_valid_data_RAM_s1}} | data_RAM_s1_readdata_from_sa) &