({32 {~cpu_0_instruction_master_read_data_valid_firmware_ROM_s1}} | firmware_ROM_s1_readdata_from_sa) &
    ({32 {~cpu_0_instruction_master_read_data_valid_payload_buffer_s1}} | {payload_buffer_s1_readdata_from_sa,
    dbs_latent_16_reg_segment_0}) &
    ({32 {~cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1}} | {incoming_tri_state_bridge_0_data,
    dbs_latent_16_reg_segment_0}) &
    ({32 {~cpu_0_instruction_master_read_data_valid_cfi_flash_1_s1}} | {incoming_tri_state_bridge_0_data,
    dbs_latent_16_reg_segment_0});

  //actual waitrequest port, which is an e_assign
  assign cpu_0_instruction_master_waitrequest = ~cpu_0_instruction_master_run;

  //latent max counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_instruction_master_latency_counter <= 0;
      else if (1)
          cpu_0_instruction_master_latency_counter <= p1_cpu_0_instruction_master_latency_counter;
    end


  //latency counter load mux, which is an e_mux
  assign p1_cpu_0_instruction_master_latency_counter = ((cpu_0_instruction_master_run & cpu_0_instruction_master_read))? latency_load_value :
    (cpu_0_instruction_master_latency_counter)? cpu_0_instruction_master_latency_counter - 1 :
    0;

  //read latency load values, which is an e_mux
  assign latency_load_value = ({2 {cpu_0_instruction_master_requests_data_RAM_s1}} & 1) |
    ({2 {cpu_0_instruction_master_requests_firmware_ROM_s1}} & 1) |
    ({2 {cpu_0_instruction_master_requests_payload_buffer_s1}} & 1) |
    ({2 {cpu_0_instruction_master_requests_cfi_flash_0_s1}} & 2) |
    ({2 {cpu_0_instruction_master_requests_cfi_flash_1_s1}} & 2);

  //input to latent dbs-16 stored 0, which is an e_mux
  assign p1_dbs_latent_16_reg_segment_0 = (cpu_0_instruction_master_read_data_valid_payload_buffer_s1)? payload_buffer_s1_readdata_from_sa :
    (cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1)? incoming_tri_state_bridge_0_data :
    incoming_tri_state_bridge_0_data;

  //dbs register for latent dbs-16 segment 0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          dbs_latent_16_reg_segment_0 <= 0;
      else if (dbs_rdv_count_enable & ((cpu_0_instruction_master_dbs_rdv_counter[1]) == 0))
          dbs_latent_16_reg_segment_0 <= p1_dbs_latent_16_reg_segment_0;
    end


  //dbs count increment, which is an e_mux
  assign cpu_0_instruction_master_dbs_increment = (cpu_0_instruction_master_requests_payload_buffer_s1)? 2 :
    (cpu_0_instruction_master_requests_cfi_flash_0_s1)? 2 :
    (cpu_0_instruction_master_requests_cfi_flash_1_s1)? 2 :
    0;

  //dbs counter overflow, which is an e_assign
  assign dbs_counter_overflow = cpu_0_instruction_master_dbs_address[1] & !(next_dbs_address[1]);

  //next master address, which is an e_assign
  assign next_dbs_address = cpu_0_instruction_master_dbs_address + cpu_0_instruction_master_dbs_increment;

  //dbs count enable, which is an e_mux
  assign dbs_count_enable = pre_dbs_count_enable;

  //dbs counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_instruction_master_dbs_address <= 0;
      else if (dbs_count_enable)
          cpu_0_instruction_master_dbs_address <= next_dbs_address;
    end


  //p1 dbs rdv counter, which is an e_assign
  assign cpu_0_instruction_master_next_dbs_rdv_counter = cpu_0_instruction_master_dbs_rdv_counter + cpu_0_instruction_master_dbs_rdv_counter_inc;

  //cpu_0_instruction_master_rdv_inc_mux, which is an e_mux
  assign cpu_0_instruction_master_dbs_rdv_counter_inc = (cpu_0_instruction_master_read_data_valid_payload_buffer_s1)? 2 :
    (cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1)? 2 :
    2;

  //master any slave rdv, which is an e_mux
  assign dbs_rdv_count_enable = cpu_0_instruction_master_read_data_valid_payload_buffer_s1 |
    cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 |
    cpu_0_instruction_master_read_data_valid_cfi_flash_1_s1;

  //dbs rdv counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_instruction_master_dbs_rdv_counter <= 0;
      else if (dbs_rdv_count_enable)
          cpu_0_instruction_master_dbs_rdv_counter <= cpu_0_instruction_master_next_dbs_rdv_counter;
    end


  //dbs rdv counter overflow, which is an e_assign
  assign dbs_rdv_counter_overflow = cpu_0_instruction_master_dbs_rdv_counter[1] & ~cpu_0_instruction_master_next_dbs_rdv_counter[1];

  //pre dbs count enable, which is an e_mux
  assign pre_dbs_count_enable = (cpu_0_instruction_master_granted_payload_buffer_s1 & cpu_0_instruction_master_read & 1 & 1) |
    ((cpu_0_instruction_master_granted_cfi_flash_0_s1 & cpu_0_instruction_master_read & 1 & 1 & ({cfi_flash_0_s1_wait_counter_eq_0 & ~d1_tri_state_bridge_0_avalon_slave_end_xfer}))) |
    ((cpu_0_instruction_master_granted_cfi_flash_1_s1 & cpu_0_instruction_master_read & 1 & 1 & ({cfi_flash_1_s1_wait_counter_eq_0 & ~d1_tri_state_bridge_0_avalon_slave_end_xfer})));


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //cpu_0_instruction_master_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_instruction_master_address_last_time <= 0;
      else if (1)
          cpu_0_instruction_master_address_last_time <= cpu_0_instruction_master_address;
    end


  //cpu_0/instruction_master waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else if (1)
          active_and_waiting_last_time <= cpu_0_instruction_master_waitrequest & (cpu_0_instruction_master_read);
    end


  //cpu_0_instruction_master_address matches last port_name, which is an e_process
  always @(active_and_waiting_last_time or cpu_0_instruction_master_address or cpu_0_instruction_master_address_last_time)
    begin
      if (active_and_waiting_last_time & (cpu_0_instruction_master_address != cpu_0_instruction_master_address_last_time))
        begin
          $write("%0d ns: cpu_0_instruction_master_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //cpu_0_instruction_master_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_instruction_master_read_last_time <= 0;
      else if (1)
          cpu_0_instruction_master_read_last_time <= cpu_0_instruction_master_read;
    end


  //cpu_0_instruction_master_read matches last port_name, which is an e_process
  always @(active_and_waiting_last_time or cpu_0_instruction_master_read or cpu_0_instruction_master_read_last_time)
    begin
      if (active_and_waiting_last_time & (cpu_0_instruction_master_read != cpu_0_instruction_master_read_last_time))
        begin
          $write("%0d ns: cpu_0_instruction_master_read did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

  // synthesis attribute cpu_0_instruction_master_arbitrator auto_dissolve FALSE

endmodule


module data_RAM_s1_arbitrator (
                                // inputs:
                                 clk,
                                 cpu_0_data_master_address_to_slave,
                                 cpu_0_data_master_byteenable,
                                 cpu_0_data_master_read,
                                 cpu_0_data_master_waitrequest,
                                 cpu_0_data_master_write,
                                 cpu_0_data_master_writedata,
                                 cpu_0_instruction_master_address_to_slave,
                                 cpu_0_instruction_master_latency_counter,
                                 cpu_0_instruction_master_read,
                                 data_RAM_s1_readdata,
                                 reset_n,

                                // outputs:
                                 cpu_0_data_master_granted_data_RAM_s1,
                                 cpu_0_data_master_qualified_request_data_RAM_s1,
                                 cpu_0_data_master_read_data_valid_data_RAM_s1,
                                 cpu_0_data_master_requests_data_RAM_s1,
                                 cpu_0_instruction_master_granted_data_RAM_s1,
                                 cpu_0_instruction_master_qualified_request_data_RAM_s1,
                                 cpu_0_instruction_master_read_data_valid_data_RAM_s1,
                                 cpu_0_instruction_master_requests_data_RAM_s1,
                                 d1_data_RAM_s1_end_xfer,
                                 data_RAM_s1_address,
                                 data_RAM_s1_byteenable,
                                 data_RAM_s1_chipselect,
                                 data_RAM_s1_clken,
                                 data_RAM_s1_readdata_from_sa,
                                 data_RAM_s1_write,
                                 data_RAM_s1_writedata,
                                 registered_cpu_0_data_master_read_data_valid_data_RAM_s1
                              );

  output           cpu_0_data_master_granted_data_RAM_s1;
  output           cpu_0_data_master_qualified_request_data_RAM_s1;
  output           cpu_0_data_master_read_data_valid_data_RAM_s1;
  output