?? up3_board.ptf
字號:
{
format = "Logic";
name = "d_readdata";
radix = "hexadecimal";
}
SIGNAL aae
{
format = "Logic";
name = "d_waitrequest";
radix = "hexadecimal";
}
SIGNAL aaf
{
format = "Logic";
name = "d_address";
radix = "hexadecimal";
}
SIGNAL aag
{
format = "Logic";
name = "d_byteenable";
radix = "hexadecimal";
}
SIGNAL aah
{
format = "Logic";
name = "d_read";
radix = "hexadecimal";
}
SIGNAL aai
{
format = "Logic";
name = "d_write";
radix = "hexadecimal";
}
SIGNAL aaj
{
format = "Logic";
name = "d_writedata";
radix = "hexadecimal";
}
SIGNAL aak
{
format = "Logic";
name = "i_readdata";
radix = "hexadecimal";
}
SIGNAL aal
{
format = "Logic";
name = "i_waitrequest";
radix = "hexadecimal";
}
SIGNAL aam
{
format = "Logic";
name = "i_address";
radix = "hexadecimal";
}
SIGNAL aan
{
format = "Logic";
name = "i_read";
radix = "hexadecimal";
}
SIGNAL aao
{
format = "Divider";
name = "common";
radix = "";
}
SIGNAL aap
{
format = "Logic";
name = "clk";
radix = "hexadecimal";
}
SIGNAL aaq
{
format = "Logic";
name = "reset_n";
radix = "hexadecimal";
}
SIGNAL aar
{
format = "Logic";
name = "F_pcb_nxt";
radix = "hexadecimal";
}
SIGNAL aas
{
format = "Logic";
name = "F_pcb";
radix = "hexadecimal";
}
SIGNAL aat
{
format = "Logic";
name = "F_vinst";
radix = "ascii";
}
SIGNAL aau
{
format = "Logic";
name = "D_vinst";
radix = "ascii";
}
SIGNAL aav
{
format = "Logic";
name = "R_vinst";
radix = "ascii";
}
SIGNAL aaw
{
format = "Logic";
name = "E_vinst";
radix = "ascii";
}
SIGNAL aax
{
format = "Logic";
name = "W_vinst";
radix = "ascii";
}
SIGNAL aay
{
format = "Logic";
name = "F_valid";
radix = "hexadecimal";
}
SIGNAL aaz
{
format = "Logic";
name = "D_valid";
radix = "hexadecimal";
}
SIGNAL aba
{
format = "Logic";
name = "R_valid";
radix = "hexadecimal";
}
SIGNAL abb
{
format = "Logic";
name = "E_valid";
radix = "hexadecimal";
}
SIGNAL abc
{
format = "Logic";
name = "W_valid";
radix = "hexadecimal";
}
SIGNAL abd
{
format = "Logic";
name = "D_wr_dst_reg";
radix = "hexadecimal";
}
SIGNAL abe
{
format = "Logic";
name = "D_dst_regnum";
radix = "hexadecimal";
}
SIGNAL abf
{
format = "Logic";
name = "W_wr_data";
radix = "hexadecimal";
}
SIGNAL abg
{
format = "Logic";
name = "F_iw";
radix = "hexadecimal";
}
SIGNAL abh
{
format = "Logic";
name = "D_iw";
radix = "hexadecimal";
}
}
}
MASTER custom_instruction_master
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "nios_custom_instruction";
Data_Width = "32";
Address_Width = "8";
Max_Address_Width = "8";
Base_Address = "N/A";
Is_Visible = "0";
Is_Custom_Instruction = "0";
Is_Enabled = "0";
}
}
}
MODULE firmware_ROM
{
class = "altera_avalon_onchip_memory2";
class_version = "4.0";
iss_model_name = "altera_memory";
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/firmware_ROM.v";
Synthesis_Only_Files = "";
}
WIZARD_SCRIPT_ARGUMENTS
{
allow_mram_sim_contents_only_file = "0";
ram_block_type = "M4K";
gui_ram_block_type = "Automatic";
Writeable = "0";
dual_port = "0";
Size_Value = "3584";
Size_Multiple = "1";
contents_info = "";
MAKE
{
TARGET delete_placeholder_warning
{
firmware_ROM
{
Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
Is_Phony = "1";
Target_File = "do_delete_placeholder_warning";
}
}
TARGET hex
{
firmware_ROM
{
Command1 = "@echo Post-processing to create $(notdir $@)";
Command2 = "elf2hex $(ELF) 0x00000000 0xDFF --width=32 $(QUARTUS_PROJECT_DIR)/firmware_ROM.hex --create-lanes=0";
Dependency = "$(ELF)";
Target_File = "$(QUARTUS_PROJECT_DIR)/firmware_ROM.hex";
}
}
TARGET sim
{
firmware_ROM
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \(Note: This does not affect the instruction set simulator.\)";
Command3 = "touch $(SIMDIR)/dummy_file";
Dependency = "$(ELF)";
Target_File = "$(SIMDIR)/dummy_file";
}
}
}
}
SYSTEM_BUILDER_INFO
{
Prohibited_Device_Family = "MERCURY, APEX20K, APEX20KE, APEX20KC, APEXII, ACEX1K, FLEX10KE, EXCALIBUR_ARM";
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Default_Module_Name = "onchip_memory";
View
{
MESSAGES
{
}
Is_Collapsed = "1";
}
}
SLAVE s1
{
PORT_WIRING
{
PORT address
{
direction = "input";
type = "address";
width = "10";
}
PORT byteenable
{
direction = "input";
type = "byteenable";
width = "4";
}
PORT chipselect
{
direction = "input";
type = "chipselect";
width = "1";
}
PORT clk
{
direction = "input";
type = "clk";
width = "1";
}
PORT debugaccess
{
direction = "input";
type = "debugaccess";
width = "1";
}
PORT readdata
{
direction = "output";
type = "readdata";
width = "32";
}
PORT write
{
direction = "input";
type = "write";
width = "1";
}
PORT writedata
{
direction = "input";
type = "writedata";
width = "32";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Memory_Device = "1";
Address_Alignment = "dynamic";
Address_Width = "10";
Data_Width = "32";
Has_IRQ = "0";
Read_Wait_States = "0";
Write_Wait_States = "0";
Address_Span = "3584";
Read_Latency = "1";
MASTERED_BY cpu_0/instruction_master
{
priority = "1";
}
MASTERED_BY cpu_0/data_master
{
priority = "1";
}
Base_Address = "0x00000000";
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "NC";
}
Is_Base_Locked = "1";
}
}
SLAVE s2
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Memory_Device = "1";
Address_Alignment = "dynamic";
Address_Width = "10";
Data_Width = "32";
Has_IRQ = "0";
Read_Wait_States = "0";
Write_Wait_States = "0";
Address_Span = "3584";
Read_Latency = "1";
Is_Enabled = "0";
}
}
SIMULATION
{
DISPLAY
{
SIGNAL a
{
name = "chipselect";
conditional = "1";
}
SIGNAL b
{
name = "write";
conditional = "1";
}
SIGNAL c
{
name = "address";
radix = "hexadecimal";
}
SIGNAL d
{
name = "byteenable";
radix = "binary";
conditional = "1";
}
SIGNAL e
{
name = "readdata";
radix = "hexadecimal";
}
SIGNAL f
{
name = "writedata";
radix = "hexadecimal";
conditional = "1";
}
}
}
PORT_WIRING
{
}
}
MODULE data_RAM
{
class = "altera_avalon_onchip_memory2";
class_version = "4.0";
iss_model_name = "altera_memory";
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/data_RAM.v";
Synthesis_Only_Files = "";
}
WIZARD_SCRIPT_ARGUMENTS
{
allow_mram_sim_contents_only_file = "0";
ram_block_type = "M4K";
gui_ram_block_type = "Automatic";
Writeable = "1";
dual_port = "0";
Size_Value = "1";
Size_Multiple = "1024";
contents_info = "QUARTUS_PROJECT_DIR/data_RAM.hex 1094974474 ";
MAKE
{
TARGET delete_placeholder_warning
{
data_RAM
{
Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
Is_Phony = "1";
Target_File = "do_delete_placeholder_warning";
}
}
TARGET hex
{
data_RAM
{
Command1 = "@echo Post-processing to create $(notdir $@)";
Command2 = "elf2hex $(ELF) 0x00010000 0x103FF --width=32 $(QUARTUS_PROJECT_DIR)/data_RAM.hex --create-lanes=0";
Dependency = "$(ELF)";
Target_File = "$(QUARTUS_PROJECT_DIR)/data_RAM.hex";
}
}
TARGET sim
{
data_RAM
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
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