//megafunction wizard: %Altera SOPC Builder%
//GENERATION: STANDARD
//VERSION: WM1.0


//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related net list (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only to
//program PLD devices (but not masked PLD devices) from Altera.  Any other
//use of such megafunction design, net list, support information, device
//programming or simulation file, or any other related documentation or
//information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
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//the intellectual property, including patents, copyrights, trademarks,
//trade secrets, or maskworks, embodied in any such megafunction design,
//net list, support information, device programming or simulation file, or
//any other related documentation or information provided by Altera or a
//megafunction partner, remains with Altera, the megafunction partner, or
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//needed under any third party's intellectual property, are provided herein.
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// exemplar translate_off
`timescale 1ns / 100ps
// exemplar translate_on
module cpu_0_data_master_arbitrator (
                                      // inputs:
                                       cfi_flash_0_s1_wait_counter_eq_0,
                                       cfi_flash_0_s1_wait_counter_eq_1,
                                       clk,
                                       cpu_0_data_master_address,
                                       cpu_0_data_master_byteenable_cfi_flash_0_s1,
                                       cpu_0_data_master_byteenable_payload_buffer_s1,
                                       cpu_0_data_master_granted_cfi_flash_0_s1,
                                       cpu_0_data_master_granted_data_RAM_s1,
                                       cpu_0_data_master_granted_firmware_ROM_s1,
                                       cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave,
                                       cpu_0_data_master_granted_payload_buffer_s1,
                                       cpu_0_data_master_granted_sysid_control_slave,
                                       cpu_0_data_master_qualified_request_cfi_flash_0_s1,
                                       cpu_0_data_master_qualified_request_data_RAM_s1,
                                       cpu_0_data_master_qualified_request_firmware_ROM_s1,
                                       cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave,
                                       cpu_0_data_master_qualified_request_payload_buffer_s1,
                                       cpu_0_data_master_qualified_request_sysid_control_slave,
                                       cpu_0_data_master_read,
                                       cpu_0_data_master_read_data_valid_cfi_flash_0_s1,
                                       cpu_0_data_master_read_data_valid_data_RAM_s1,
                                       cpu_0_data_master_read_data_valid_firmware_ROM_s1,
                                       cpu_0_data_master_read_data_valid_payload_buffer_s1,
                                       cpu_0_data_master_requests_cfi_flash_0_s1,
                                       cpu_0_data_master_requests_data_RAM_s1,
                                       cpu_0_data_master_requests_firmware_ROM_s1,
                                       cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave,
                                       cpu_0_data_master_requests_payload_buffer_s1,
                                       cpu_0_data_master_requests_sysid_control_slave,
                                       cpu_0_data_master_s_turn_at_cfi_flash_0_s1,
                                       cpu_0_data_master_s_turn_at_data_RAM_s1,
                                       cpu_0_data_master_s_turn_at_firmware_ROM_s1,
                                       cpu_0_data_master_s_turn_at_payload_buffer_s1,
                                       cpu_0_data_master_write,
                                       cpu_0_data_master_writedata,
                                       cpu_0_instruction_master_qualified_request_cfi_flash_0_s1,
                                       cpu_0_instruction_master_qualified_request_data_RAM_s1,
                                       cpu_0_instruction_master_qualified_request_firmware_ROM_s1,
                                       cpu_0_instruction_master_qualified_request_payload_buffer_s1,
                                       d1_cpu_0_data_master_granted_cfi_flash_0_s1,
                                       d1_cpu_0_data_master_granted_data_RAM_s1,
                                       d1_cpu_0_data_master_granted_firmware_ROM_s1,
                                       d1_cpu_0_data_master_granted_payload_buffer_s1,
                                       d1_data_RAM_s1_end_xfer,
                                       d1_firmware_ROM_s1_end_xfer,
                                       d1_jtag_uart_0_avalon_jtag_slave_end_xfer,
                                       d1_payload_buffer_s1_end_xfer,
                                       d1_sysid_control_slave_end_xfer,
                                       d1_tri_state_bridge_0_avalon_slave_end_xfer,
                                       d2_reset_n,
                                       data_RAM_s1_readdata_from_sa,
                                       firmware_ROM_s1_readdata_from_sa,
                                       incoming_tri_state_bridge_0_data_with_Xs_converted_to_0,
                                       jtag_uart_0_avalon_jtag_slave_irq_from_sa,
                                       jtag_uart_0_avalon_jtag_slave_readdata_from_sa,
                                       jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa,
                                       payload_buffer_s1_readdata_from_sa,
                                       registered_cpu_0_data_master_read_data_valid_cfi_flash_0_s1,
                                       registered_cpu_0_data_master_read_data_valid_data_RAM_s1,
                                       registered_cpu_0_data_master_read_data_valid_firmware_ROM_s1,
                                       registered_cpu_0_data_master_read_data_valid_payload_buffer_s1,
                                       sysid_control_slave_readdata_from_sa,

                                      // outputs:
                                       cpu_0_data_master_address_to_slave,
                                       cpu_0_data_master_dbs_address,
                                       cpu_0_data_master_dbs_write_16,
                                       cpu_0_data_master_irq,
                                       cpu_0_data_master_no_byte_enables_and_last_term,
                                       cpu_0_data_master_readdata,
                                       cpu_0_data_master_reset_n,
                                       cpu_0_data_master_waitrequest
                                    );

  output  [ 21: 0] cpu_0_data_master_address_to_slave;
  output  [  1: 0] cpu_0_data_master_dbs_address;
  output  [ 15: 0] cpu_0_data_master_dbs_write_16;
  output  [ 31: 0] cpu_0_data_master_irq;
  output           cpu_0_data_master_no_byte_enables_and_last_term;
  output  [ 31: 0] cpu_0_data_master_readdata;
  output           cpu_0_data_master_reset_n;
  output           cpu_0_data_master_waitrequest;
  input            cfi_flash_0_s1_wait_counter_eq_0;
  input            cfi_flash_0_s1_wait_counter_eq_1;
  input            clk;
  input   [ 21: 0] cpu_0_data_master_address;
  input   [  1: 0] cpu_0_data_master_byteenable_cfi_flash_0_s1;
  input   [  1: 0] cpu_0_data_master_byteenable_payload_buffer_s1;
  input            cpu_0_data_master_granted_cfi_flash_0_s1;
  input            cpu_0_data_master_granted_data_RAM_s1;
  input            cpu_0_data_master_granted_firmware_ROM_s1;
  input            cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave;
  input            cpu_0_data_master_granted_payload_buffer_s1;
  input            cpu_0_data_master_granted_sysid_control_slave;
  input            cpu_0_data_master_qualified_request_cfi_flash_0_s1;
  input            cpu_0_data_master_qualified_request_data_RAM_s1;
  input            cpu_0_data_master_qualified_request_firmware_ROM_s1;
  input            cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave;
  input            cpu_0_data_master_qualified_request_payload_buffer_s1;
  input            cpu_0_data_master_qualified_request_sysid_control_slave;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_read_data_valid_cfi_flash_0_s1;
  input            cpu_0_data_master_read_data_valid_data_RAM_s1;
  input            cpu_0_data_master_read_data_valid_firmware_ROM_s1;
  input            cpu_0_data_master_read_data_valid_payload_buffer_s1;
  input            cpu_0_data_master_requests_cfi_flash_0_s1;
  input            cpu_0_data_master_requests_data_RAM_s1;
  input            cpu_0_data_master_requests_firmware_ROM_s1;
  input            cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave;
  input            cpu_0_data_master_requests_payload_buffer_s1;
  input            cpu_0_data_master_requests_sysid_control_slave;
  input            cpu_0_data_master_s_turn_at_cfi_flash_0_s1;
  input            cpu_0_data_master_s_turn_at_data_RAM_s1;
  input            cpu_0_data_master_s_turn_at_firmware_ROM_s1;
  input            cpu_0_data_master_s_turn_at_payload_buffer_s1;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input            cpu_0_instruction_master_qualified_request_cfi_flash_0_s1;
  input            cpu_0_instruction_master_qualified_request_data_RAM_s1;
  input            cpu_0_instruction_master_qualified_request_firmware_ROM_s1;
  input            cpu_0_instruction_master_qualified_request_payload_buffer_s1;
  input            d1_cpu_0_data_master_granted_cfi_flash_0_s1;
  input            d1_cpu_0_data_master_granted_data_RAM_s1;
  input            d1_cpu_0_data_master_granted_firmware_ROM_s1;
  input            d1_cpu_0_data_master_granted_payload_buffer_s1;
  input            d1_data_RAM_s1_end_xfer;
  input            d1_firmware_ROM_s1_end_xfer;
  input            d1_jtag_uart_0_avalon_jtag_slave_end_xfer;
  input            d1_payload_buffer_s1_end_xfer;
  input            d1_sysid_control_slave_end_xfer;
  input            d1_tri_state_bridge_0_avalon_slave_end_xfer;
  input            d2_reset_n;
  input   [ 31: 0] data_RAM_s1_readdata_from_sa;
  input   [ 31: 0] firmware_ROM_s1_readdata_from_sa;
  input   [ 15: 0] incoming_tri_state_bridge_0_data_with_Xs_converted_to_0;
  input            jtag_uart_0_avalon_jtag_slave_irq_from_sa;
  input   [ 31: 0] jtag_uart_0_avalon_jtag_slave_readdata_from_sa;
  input            jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa;
  input   [ 15: 0] payload_buffer_s1_readdata_from_sa;
  input            registered_cpu_0_data_master_read_data_valid_cfi_flash_0_s1;
  input            registered_cpu_0_data_master_read_data_valid_data_RAM_s1;
  input            registered_cpu_0_data_master_read_data_valid_firmware_ROM_s1;
  input            registered_cpu_0_data_master_read_data_valid_payload_buffer_s1;
  input   [ 31: 0] sysid_control_slave_readdata_from_sa;

  wire    [ 21: 0] cpu_0_data_master_address_to_slave;
  reg     [  1: 0] cpu_0_data_master_dbs_address;
  wire    [  1: 0] cpu_0_data_master_dbs_increment;
  wire    [ 15: 0] cpu_0_data_master_dbs_write_16;
  wire    [ 31: 0] cpu_0_data_master_irq;
  reg              cpu_0_data_master_no_byte_enables_and_last_term;
  wire    [ 31: 0] cpu_0_data_master_readdata;
  wire             cpu_0_data_master_reset_n;
  reg              cpu_0_data_master_waitrequest;
  reg     [ 15: 0] dbs_16_reg_segment_0;
  wire             dbs_count_enable;
  wire             dbs_counter_overflow;
  wire             dummy_sink;
  wire             last_dbs_term_and_run;
  wire    [  1: 0] next_dbs_address;
  wire             p1_cpu_0_data_master_waitrequest;
  wire    [ 15: 0] p1_dbs_16_reg_segment_0;
  wire    [ 31: 0] p1_registered_cpu_0_data_master_readdata;
  wire             pre_dbs_count_enable;
  wire             r_0;
  wire             r_1;
  reg     [ 31: 0] registered_cpu_0_data_master_readdata;
  //r_0 cascaded wait assignment, which is an e_assign
  assign r_0 = (cpu_0_data_master_qualified_request_data_RAM_s1 | registered_cpu_0_data_master_read_data_valid_data_RAM_s1 | ~cpu_0_data_master_requests_data_RAM_s1) & (!cpu_0_data_master_qualified_request_data_RAM_s1 |
    (cpu_0_data_master_qualified_request_data_RAM_s1 &
    (!cpu_0_instruction_master_qualified_request_data_RAM_s1 |
    (cpu_0_instruction_master_qualified_request_data_RAM_s1 &
    ((d1_data_RAM_s1_end_xfer)?
    cpu_0_data_master_s_turn_at_data_RAM_s1: d1_cpu_0_data_master_granted_data_RAM_s1
    )
    )
    )
    )) & ((~cpu_0_data_master_qualified_request_data_RAM_s1 | ~cpu_0_data_master_read | (registered_cpu_0_data_master_read_data_valid_data_RAM_s1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_data_RAM_s1 | ~cpu_0_data_master_write | (1 & cpu_0_data_master_write))) & (cpu_0_data_master_qualified_request_firmware_ROM_s1 | registered_cpu_0_data_master_read_data_valid_firmware_ROM_s1 | ~cpu_0_data_master_requests_firmware_ROM_s1) & (!cpu_0_data_master_qualified_request_firmware_ROM_s1 |
    (cpu_0_data_master_qualified_request_firmware_ROM_s1 &
    (!cpu_0_instruction_master_qualified_request_firmware_ROM_s1 |
    (cpu_0_instruction_master_qualified_request_firmware_ROM_s1 &
    ((d1_firmware_ROM_s1_end_xfer)?
    cpu_0_data_master_s_turn_at_firmware_ROM_s1: d1_cpu_0_data_master_granted_firmware_ROM_s1
    )
    )