else if (1)
          d1_cpu_0_data_master_granted_data_RAM_s1 <= cpu_0_data_master_granted_data_RAM_s1;
    end


  //d1_cpu_0_instruction_master_granted_data_RAM_s1 register granted, which is an e_register
  always @(posedge clk or negedge d2_reset_n)
    begin
      if (d2_reset_n == 0)
          d1_cpu_0_instruction_master_granted_data_RAM_s1 <= 0;
      else if (1)
          d1_cpu_0_instruction_master_granted_data_RAM_s1 <= cpu_0_instruction_master_granted_data_RAM_s1;
    end


  assign data_RAM_s1_chipselect = cpu_0_data_master_granted_data_RAM_s1 | cpu_0_instruction_master_granted_data_RAM_s1;
  //data_RAM_s1_address mux, which is an e_mux
  assign data_RAM_s1_address = (cpu_0_data_master_granted_data_RAM_s1)? (cpu_0_data_master_address_to_slave >> 2) :
    (cpu_0_instruction_master_address_to_slave >> 2);

  //data_RAM_s1_write assignment, which is an e_mux
  assign data_RAM_s1_write = cpu_0_data_master_granted_data_RAM_s1 & cpu_0_data_master_write;

  assign data_RAM_s1_waits_for_read = data_RAM_s1_in_a_read_cycle & 0;
  //data_RAM_s1_in_a_read_cycle assignment, which is an e_assign
  assign data_RAM_s1_in_a_read_cycle = (cpu_0_data_master_granted_data_RAM_s1 & cpu_0_data_master_read) | (cpu_0_instruction_master_granted_data_RAM_s1 & cpu_0_instruction_master_read);

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = data_RAM_s1_in_a_read_cycle;

  assign data_RAM_s1_waits_for_write = data_RAM_s1_in_a_write_cycle & 0;
  //data_RAM_s1_in_a_write_cycle assignment, which is an e_assign
  assign data_RAM_s1_in_a_write_cycle = cpu_0_data_master_granted_data_RAM_s1 & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = data_RAM_s1_in_a_write_cycle;

  assign wait_for_data_RAM_s1_counter = 0;
  //data_RAM_s1_byteenable mux, which is an e_mux
  assign data_RAM_s1_byteenable = (cpu_0_data_master_granted_data_RAM_s1)? cpu_0_data_master_byteenable :
    -1;


  // exemplar attribute data_RAM_s1_arbitrator auto_dissolve FALSE

endmodule


module firmware_ROM_s1_arbitrator (
                                    // inputs:
                                     clk,
                                     cpu_0_data_master_address_to_slave,
                                     cpu_0_data_master_byteenable,
                                     cpu_0_data_master_read,
                                     cpu_0_data_master_waitrequest,
                                     cpu_0_data_master_write,
                                     cpu_0_data_master_writedata,
                                     cpu_0_instruction_master_address_to_slave,
                                     cpu_0_instruction_master_read,
                                     d2_reset_n,
                                     firmware_ROM_s1_readdata,

                                    // outputs:
                                     cpu_0_data_master_granted_firmware_ROM_s1,
                                     cpu_0_data_master_qualified_request_firmware_ROM_s1,
                                     cpu_0_data_master_read_data_valid_firmware_ROM_s1,
                                     cpu_0_data_master_requests_firmware_ROM_s1,
                                     cpu_0_data_master_s_turn_at_firmware_ROM_s1,
                                     cpu_0_instruction_master_granted_firmware_ROM_s1,
                                     cpu_0_instruction_master_qualified_request_firmware_ROM_s1,
                                     cpu_0_instruction_master_read_data_valid_firmware_ROM_s1,
                                     cpu_0_instruction_master_requests_firmware_ROM_s1,
                                     d1_cpu_0_data_master_granted_firmware_ROM_s1,
                                     d1_cpu_0_instruction_master_granted_firmware_ROM_s1,
                                     d1_firmware_ROM_s1_end_xfer,
                                     firmware_ROM_s1_address,
                                     firmware_ROM_s1_byteenable,
                                     firmware_ROM_s1_chipselect,
                                     firmware_ROM_s1_readdata_from_sa,
                                     firmware_ROM_s1_write,
                                     firmware_ROM_s1_writedata,
                                     registered_cpu_0_data_master_read_data_valid_firmware_ROM_s1
                                  );

  output           cpu_0_data_master_granted_firmware_ROM_s1;
  output           cpu_0_data_master_qualified_request_firmware_ROM_s1;
  output           cpu_0_data_master_read_data_valid_firmware_ROM_s1;
  output           cpu_0_data_master_requests_firmware_ROM_s1;
  output           cpu_0_data_master_s_turn_at_firmware_ROM_s1;
  output           cpu_0_instruction_master_granted_firmware_ROM_s1;
  output           cpu_0_instruction_master_qualified_request_firmware_ROM_s1;
  output           cpu_0_instruction_master_read_data_valid_firmware_ROM_s1;
  output           cpu_0_instruction_master_requests_firmware_ROM_s1;
  output           d1_cpu_0_data_master_granted_firmware_ROM_s1;
  output           d1_cpu_0_instruction_master_granted_firmware_ROM_s1;
  output           d1_firmware_ROM_s1_end_xfer;
  output  [  9: 0] firmware_ROM_s1_address;
  output  [  3: 0] firmware_ROM_s1_byteenable;
  output           firmware_ROM_s1_chipselect;
  output  [ 31: 0] firmware_ROM_s1_readdata_from_sa;
  output           firmware_ROM_s1_write;
  output  [ 31: 0] firmware_ROM_s1_writedata;
  output           registered_cpu_0_data_master_read_data_valid_firmware_ROM_s1;
  input            clk;
  input   [ 21: 0] cpu_0_data_master_address_to_slave;
  input   [  3: 0] cpu_0_data_master_byteenable;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_waitrequest;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input   [ 21: 0] cpu_0_instruction_master_address_to_slave;
  input            cpu_0_instruction_master_read;
  input            d2_reset_n;
  input   [ 31: 0] firmware_ROM_s1_readdata;

  wire             cpu_0_data_master_granted_firmware_ROM_s1;
  wire             cpu_0_data_master_qualified_request_firmware_ROM_s1;
  wire             cpu_0_data_master_read_data_valid_firmware_ROM_s1;
  reg              cpu_0_data_master_read_data_valid_firmware_ROM_s1_shift_register;
  wire             cpu_0_data_master_read_data_valid_firmware_ROM_s1_shift_register_in;
  wire             cpu_0_data_master_requests_firmware_ROM_s1;
  reg              cpu_0_data_master_s_turn_at_firmware_ROM_s1;
  wire             cpu_0_instruction_master_granted_firmware_ROM_s1;
  wire             cpu_0_instruction_master_qualified_request_firmware_ROM_s1;
  wire             cpu_0_instruction_master_read_data_valid_firmware_ROM_s1;
  reg              cpu_0_instruction_master_read_data_valid_firmware_ROM_s1_shift_register;
  wire             cpu_0_instruction_master_read_data_valid_firmware_ROM_s1_shift_register_in;
  wire             cpu_0_instruction_master_requests_firmware_ROM_s1;
  reg              d1_cpu_0_data_master_granted_firmware_ROM_s1;
  reg              d1_cpu_0_instruction_master_granted_firmware_ROM_s1;
  reg              d1_firmware_ROM_s1_end_xfer;
  wire    [  9: 0] firmware_ROM_s1_address;
  wire    [  3: 0] firmware_ROM_s1_byteenable;
  wire             firmware_ROM_s1_chipselect;
  wire             firmware_ROM_s1_end_xfer;
  wire             firmware_ROM_s1_in_a_read_cycle;
  wire             firmware_ROM_s1_in_a_write_cycle;
  wire    [ 31: 0] firmware_ROM_s1_readdata_from_sa;
  wire             firmware_ROM_s1_waits_for_read;
  wire             firmware_ROM_s1_waits_for_write;
  wire             firmware_ROM_s1_write;
  wire    [ 31: 0] firmware_ROM_s1_writedata;
  reg              grant_0;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             next_grant_0;
  wire             p1_cpu_0_data_master_read_data_valid_firmware_ROM_s1_shift_register;
  wire             p1_cpu_0_instruction_master_read_data_valid_firmware_ROM_s1_shift_register;
  wire             registered_cpu_0_data_master_read_data_valid_firmware_ROM_s1;
  wire             wait_for_firmware_ROM_s1_counter;
  //cpu_0_data_master_granted_firmware_ROM_s1 granted, which is an e_assign
  assign cpu_0_data_master_granted_firmware_ROM_s1 = cpu_0_data_master_qualified_request_firmware_ROM_s1 &
    (!cpu_0_instruction_master_qualified_request_firmware_ROM_s1 |
    (
    ((d1_firmware_ROM_s1_end_xfer)?
    cpu_0_data_master_s_turn_at_firmware_ROM_s1 : d1_cpu_0_data_master_granted_firmware_ROM_s1
    )
    )
    );

  //cpu_0_instruction_master_granted_firmware_ROM_s1 granted, which is an e_assign
  assign cpu_0_instruction_master_granted_firmware_ROM_s1 = cpu_0_instruction_master_qualified_request_firmware_ROM_s1 &
    (!cpu_0_data_master_qualified_request_firmware_ROM_s1 |
    (
    ((d1_firmware_ROM_s1_end_xfer)?
    (!cpu_0_data_master_s_turn_at_firmware_ROM_s1) : d1_cpu_0_instruction_master_granted_firmware_ROM_s1
    )
    )
    );

  assign cpu_0_data_master_requests_firmware_ROM_s1 = ({cpu_0_data_master_address_to_slave[21 : 12] , 12'b0} == 22'h0) & (cpu_0_data_master_read | cpu_0_data_master_write);
  //assign firmware_ROM_s1_readdata_from_sa = firmware_ROM_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign firmware_ROM_s1_readdata_from_sa = firmware_ROM_s1_readdata;

  //registered rdv signal_name registered_cpu_0_data_master_read_data_valid_firmware_ROM_s1 assignment, which is an e_assign
  assign registered_cpu_0_data_master_read_data_valid_firmware_ROM_s1 = cpu_0_data_master_read_data_valid_firmware_ROM_s1_shift_register_in;

  assign cpu_0_data_master_qualified_request_firmware_ROM_s1 = cpu_0_data_master_requests_firmware_ROM_s1 & ~((cpu_0_data_master_read & ((|cpu_0_data_master_read_data_valid_firmware_ROM_s1_shift_register))) | ((~cpu_0_data_master_waitrequest) & cpu_0_data_master_write));
  assign cpu_0_data_master_read_data_valid_firmware_ROM_s1_shift_register_in = cpu_0_data_master_granted_firmware_ROM_s1 & cpu_0_data_master_read & ~firmware_ROM_s1_waits_for_read & ~(|cpu_0_data_master_read_data_valid_firmware_ROM_s1_shift_register);
  assign p1_cpu_0_data_master_read_data_valid_firmware_ROM_s1_shift_register = {cpu_0_data_master_read_data_valid_firmware_ROM_s1_shift_register, cpu_0_data_master_read_data_valid_firmware_ROM_s1_shift_register_in};
  always @(posedge clk or negedge d2_reset_n)
    begin
      if (d2_reset_n == 0)
          cpu_0_data_master_read_data_valid_firmware_ROM_s1_shift_register <= 0;
      else if (1)
          cpu_0_data_master_read_data_valid_firmware_ROM_s1_shift_register <= p1_cpu_0_data_master_read_data_valid_firmware_ROM_s1_shift_register;
    end


  assign cpu_0_data_master_read_data_valid_firmware_ROM_s1 = cpu_0_data_master_read_data_valid_firmware_ROM_s1_shift_register;
  //firmware_ROM_s1_writedata mux, which is an e_mux
  assign firmware_ROM_s1_writedata = cpu_0_data_master_writedata;

  assign cpu_0_instruction_master_requests_firmware_ROM_s1 = ({cpu_0_instruction_master_address_to_slave[21 : 12] , 12'b0} == 22'h0) & (cpu_0_instruction_master_read);
  assign cpu_0_instruction_master_qualified_request_firmware_ROM_s1 = cpu_0_instruction_master_requests_firmware_ROM_s1 & ~((cpu_0_instruction_master_read & ((|cpu_0_instruction_master_read_data_valid_firmware_ROM_s1_shift_register))));
  assign cpu_0_instruction_master_read_data_valid_firmware_ROM_s1_shift_register_in = cpu_0_instruction_master_granted_firmware_ROM_s1 & cpu_0_instruction_master_read & ~firmware_ROM_s1_waits_for_read & ~(|cpu_0_instruction_master_read_data_valid_firmware_ROM_s1_shift_register);
  assign p1_cpu_0_instruction_master_read_data_valid_firmware_ROM_s1_shift_register = {cpu_0_instruction_master_read_data_valid_firmware_ROM_s1_shift_register, cpu_0_instruction_master_read_data_valid_firmware_ROM_s1_shift_register_in};
  always @(posedge clk or negedge d2_reset_n)
    begin
      if (d2_reset_n == 0)
          cpu_0_instruction_master_read_data_valid_firmware_ROM_s1_shift_register <= 0;
      else if (1)
          cpu_0_instruction_master_read_data_valid_firmware_ROM_s1_shift_register <= p1_cpu_0_instruction_master_read_data_valid_firmware_ROM_s1_shift_register;
    end


  assign cpu_0_instruction_master_read_data_valid_firmware_ROM_s1 = cpu_0_instruction_master_read_data_valid_firmware_ROM_s1_shift_register;
  //arbitration next grant 0 assignment, which is an e_assign
  assign next_grant_0 = (grant_0 == 1) ? 0 : (grant_0 + 1);

  //firmware_ROM_s1_end_xfer assignment, which is an e_assign
  assign firmware_ROM_s1_end_xfer = ~(firmware_ROM_s1_waits_for_read | firmware_ROM_s1_waits_for_write);

  //cpu_0/data_master gets granted 1
  //out of 2 times contention occurs
  always @(posedge clk or negedge d2_r