Analysis & Synthesis report for UP3_Board
Sun Sep 12 18:46:05 2004
Version 4.1 Build 181 06/29/2004 SJ Web Edition


---------------------
; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Multiplexer Restructuring Statistics (No Restructuring Performed)
  5. WYSIWYG Cells
  6. General Register Statistics
  7. Hierarchy
  8. State Machine - UP3_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|a_fffifo:subfifo|a_fefifo:fifo_state|sm_emptyfull
  9. State Machine - UP3_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|a_fffifo:subfifo|a_fefifo:fifo_state|sm_emptyfull
 10. Analysis & Synthesis Resource Utilization by Entity
 11. Analysis & Synthesis Equations
 12. Analysis & Synthesis Source Files Read
 13. Analysis & Synthesis Resource Usage Summary
 14. Analysis & Synthesis RAM Summary
 15. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+-----------------------------------------------------------------------+
; Analysis & Synthesis Summary                                          ;
+-----------------------------+-----------------------------------------+
; Analysis & Synthesis Status ; Successful - Sun Sep 12 18:46:05 2004   ;
; Quartus II Version          ; 4.1 Build 181 06/29/2004 SJ Web Edition ;
; Revision Name               ; UP3_Board                               ;
; Top-level Entity Name       ; UP3_Board_top                           ;
; Family                      ; Cyclone                                 ;
; Total logic elements        ; 2,973                                   ;
; Total pins                  ; 48                                      ;
; Total memory bits           ; 70,656                                  ;
; Total PLLs                  ; 0                                       ;
+-----------------------------+-----------------------------------------+


+----------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                      ;
+--------------------------------------------------------------------+---------------+---------------+
; Option                                                             ; Setting       ; Default Value ;
+--------------------------------------------------------------------+---------------+---------------+
; Device                                                             ; EP1C6Q240C8   ;               ;
; Family name                                                        ; Cyclone       ; Stratix       ;
; Top-level entity name                                              ; UP3_Board_top ; UP3_Board     ;
; Restructure Multiplexers                                           ; Auto          ; Auto          ;
; Create Debugging Nodes for IP Cores                                ; off           ; off           ;
; Disk space/compilation speed tradeoff                              ; Normal        ; Normal        ;
; Preserve fewer node names                                          ; On            ; On            ;
; Disable OpenCore Plus hardware evaluation                          ; Off           ; Off           ;
; Verilog Version                                                    ; Verilog_2001  ; Verilog_2001  ;
; VHDL Version                                                       ; VHDL93        ; VHDL93        ;
; State Machine Processing                                           ; Auto          ; Auto          ;
; NOT Gate Push-Back                                                 ; On            ; On            ;
; Power-Up Don't Care                                                ; On            ; On            ;
; Remove Redundant Logic Cells                                       ; Off           ; Off           ;
; Remove Duplicate Registers                                         ; On            ; On            ;
; Ignore CARRY Buffers                                               ; Off           ; Off           ;
; Ignore CASCADE Buffers                                             ; Off           ; Off           ;
; Ignore GLOBAL Buffers                                              ; Off           ; Off           ;
; Ignore ROW GLOBAL Buffers                                          ; Off           ; Off           ;
; Ignore LCELL Buffers                                               ; Off           ; Off           ;
; Ignore SOFT Buffers                                                ; On            ; On            ;
; Limit AHDL Integers to 32 Bits                                     ; Off           ; Off           ;
; Optimization Technique -- Cyclone                                  ; Balanced      ; Balanced      ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70            ; 70            ;
; Auto Carry Chains                                                  ; On            ; On            ;
; Auto Open-Drain Pins                                               ; On            ; On            ;
; Remove Duplicate Logic                                             ; On            ; On            ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off           ; Off           ;
; Perform gate-level register retiming                               ; Off           ; Off           ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On            ; On            ;
; Auto ROM Replacement                                               ; On            ; On            ;
; Auto RAM Replacement                                               ; On            ; On            ;
; Auto Shift Register Replacement                                    ; On            ; On            ;
; Auto Clock Enable Replacement                                      ; On            ; On            ;