--S1_write_n_to_the_cfi_flash_0 is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|write_n_to_the_cfi_flash_0
--operation mode is normal

S1_write_n_to_the_cfi_flash_0_lut_out = S1L11 & !S1L99 & (S1_cfi_flash_0_s1_wait_counter[3] $ !S1L1);
S1_write_n_to_the_cfi_flash_0 = DFFEA(S1_write_n_to_the_cfi_flash_0_lut_out, clk, B1_d2_reset_n, , , , );


--S1_tri_state_bridge_0_readn is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_readn
--operation mode is normal

S1_tri_state_bridge_0_readn_lut_out = !S1L99 & !S1_cfi_flash_0_s1_wait_counter[3] & (S1L13 # S1L01);
S1_tri_state_bridge_0_readn = DFFEA(S1_tri_state_bridge_0_readn_lut_out, clk, B1_d2_reset_n, , , , );


--S1_select_n_to_the_cfi_flash_0 is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|select_n_to_the_cfi_flash_0
--operation mode is normal

S1_select_n_to_the_cfi_flash_0_lut_out = S1L13 # S1_cpu_0_data_master_qualified_request_cfi_flash_0_s1 & !S1L02;
S1_select_n_to_the_cfi_flash_0 = DFFEA(S1_select_n_to_the_cfi_flash_0_lut_out, clk, B1_d2_reset_n, , , , );


--S1_tri_state_bridge_0_address[20] is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[20]
--operation mode is normal

S1_tri_state_bridge_0_address[20]_lut_out = D1_W_alu_result[20] & (D1_F_pc[18] # S1L12) # !D1_W_alu_result[20] & D1_F_pc[18] & !S1L12;
S1_tri_state_bridge_0_address[20] = DFFEA(S1_tri_state_bridge_0_address[20]_lut_out, clk, B1_d2_reset_n, , , , );


--S1_tri_state_bridge_0_address[19] is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[19]
--operation mode is normal

S1_tri_state_bridge_0_address[19]_lut_out = D1_W_alu_result[19] & (D1_F_pc[17] # S1L12) # !D1_W_alu_result[19] & D1_F_pc[17] & !S1L12;
S1_tri_state_bridge_0_address[19] = DFFEA(S1_tri_state_bridge_0_address[19]_lut_out, clk, B1_d2_reset_n, , , , );


--S1_tri_state_bridge_0_address[18] is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[18]
--operation mode is normal

S1_tri_state_bridge_0_address[18]_lut_out = D1_W_alu_result[18] & (D1_F_pc[16] # S1L12) # !D1_W_alu_result[18] & D1_F_pc[16] & !S1L12;
S1_tri_state_bridge_0_address[18] = DFFEA(S1_tri_state_bridge_0_address[18]_lut_out, clk, B1_d2_reset_n, , , , );


--S1_tri_state_bridge_0_address[17] is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[17]
--operation mode is normal

S1_tri_state_bridge_0_address[17]_lut_out = D1_W_alu_result[17] & (D1_F_pc[15] # S1L12) # !D1_W_alu_result[17] & D1_F_pc[15] & !S1L12;
S1_tri_state_bridge_0_address[17] = DFFEA(S1_tri_state_bridge_0_address[17]_lut_out, clk, B1_d2_reset_n, , , , );


--S1_tri_state_bridge_0_address[16] is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[16]
--operation mode is normal

S1_tri_state_bridge_0_address[16]_lut_out = D1_W_alu_result[16] & (D1_F_pc[14] # S1L12) # !D1_W_alu_result[16] & D1_F_pc[14] & !S1L12;
S1_tri_state_bridge_0_address[16] = DFFEA(S1_tri_state_bridge_0_address[16]_lut_out, clk, B1_d2_reset_n, , , , );


--S1_tri_state_bridge_0_address[15] is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[15]
--operation mode is normal

S1_tri_state_bridge_0_address[15]_lut_out = D1_W_alu_result[15] & (D1_F_pc[13] # S1L12) # !D1_W_alu_result[15] & D1_F_pc[13] & !S1L12;
S1_tri_state_bridge_0_address[15] = DFFEA(S1_tri_state_bridge_0_address[15]_lut_out, clk, B1_d2_reset_n, , , , );


--S1_tri_state_bridge_0_address[14] is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[14]
--operation mode is normal

S1_tri_state_bridge_0_address[14]_lut_out = D1_W_alu_result[14] & (D1_F_pc[12] # S1L12) # !D1_W_alu_result[14] & D1_F_pc[12] & !S1L12;
S1_tri_state_bridge_0_address[14] = DFFEA(S1_tri_state_bridge_0_address[14]_lut_out, clk, B1_d2_reset_n, , , , );


--S1_tri_state_bridge_0_address[13] is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[13]
--operation mode is normal

S1_tri_state_bridge_0_address[13]_lut_out = D1_W_alu_result[13] & (D1_F_pc[11] # S1L12) # !D1_W_alu_result[13] & D1_F_pc[11] & !S1L12;
S1_tri_state_bridge_0_address[13] = DFFEA(S1_tri_state_bridge_0_address[13]_lut_out, clk, B1_d2_reset_n, , , , );


--S1_tri_state_bridge_0_address[12] is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[12]
--operation mode is normal

S1_tri_state_bridge_0_address[12]_lut_out = D1_W_alu_result[12] & (D1_F_pc[10] # S1L12) # !D1_W_alu_result[12] & D1_F_pc[10] & !S1L12;
S1_tri_state_bridge_0_address[12] = DFFEA(S1_tri_state_bridge_0_address[12]_lut_out, clk, B1_d2_reset_n, , , , );


--S1_tri_state_bridge_0_address[11] is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[11]
--operation mode is normal

S1_tri_state_bridge_0_address[11]_lut_out = D1_W_alu_result[11] & (D1_F_pc[9] # S1L12) # !D1_W_alu_result[11] & D1_F_pc[9] & !S1L12;
S1_tri_state_bridge_0_address[11] = DFFEA(S1_tri_state_bridge_0_address[11]_lut_out, clk, B1_d2_reset_n, , , , );


--S1_tri_state_bridge_0_address[10] is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[10]
--operation mode is normal

S1_tri_state_bridge_0_address[10]_lut_out = D1_W_alu_result[10] & (D1_F_pc[8] # S1L12) # !D1_W_alu_result[10] & D1_F_pc[8] & !S1L12;
S1_tri_state_bridge_0_address[10] = DFFEA(S1_tri_state_bridge_0_address[10]_lut_out, clk, B1_d2_reset_n, , , , );


--S1_tri_state_bridge_0_address[9] is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[9]
--operation mode is normal

S1_tri_state_bridge_0_address[9]_lut_out = D1_W_alu_result[9] & (D1_F_pc[7] # S1L12) # !D1_W_alu_result[9] & D1_F_pc[7] & !S1L12;
S1_tri_state_bridge_0_address[9] = DFFEA(S1_tri_state_bridge_0_address[9]_lut_out, clk, B1_d2_reset_n, , , , );


--S1_tri_state_bridge_0_address[8] is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[8]
--operation mode is normal

S1_tri_state_bridge_0_address[8]_lut_out = D1_W_alu_result[8] & (D1_F_pc[6] # S1L12) # !D1_W_alu_result[8] & D1_F_pc[6] & !S1L12;
S1_tri_state_bridge_0_address[8] = DFFEA(S1_tri_state_bridge_0_address[8]_lut_out, clk, B1_d2_reset_n, , , , );


--S1_tri_state_bridge_0_address[7] is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[7]
--operation mode is normal

S1_tri_state_bridge_0_address[7]_lut_out = D1_W_alu_result[7] & (D1_F_pc[5] # S1L12) # !D1_W_alu_result[7] & D1_F_pc[5] & !S1L12;
S1_tri_state_bridge_0_address[7] = DFFEA(S1_tri_state_bridge_0_address[7]_lut_out, clk, B1_d2_reset_n, , , , );


--S1_tri_state_bridge_0_address[6] is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[6]
--operation mode is normal

S1_tri_state_bridge_0_address[6]_lut_out = D1_W_alu_result[6] & (D1_F_pc[4] # S1L12) # !D1_W_alu_result[6] & D1_F_pc[4] & !S1L12;
S1_tri_state_bridge_0_address[6] = DFFEA(S1_tri_state_bridge_0_address[6]_lut_out, clk, B1_d2_reset_n, , , , );


--S1_tri_state_bridge_0_address[5] is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[5]
--operation mode is normal

S1_tri_state_bridge_0_address[5]_lut_out = D1_W_alu_result[5] & (D1_F_pc[3] # S1L12) # !D1_W_alu_result[5] & D1_F_pc[3] & !S1L12;
S1_tri_state_bridge_0_address[5] = DFFEA(S1_tri_state_bridge_0_address[5]_lut_out, clk, B1_d2_reset_n, , , , );


--S1_tri_state_bridge_0_address[4] is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[4]
--operation mode is normal

S1_tri_state_bridge_0_address[4]_lut_out = D1_W_alu_result[4] & (D1_F_pc[2] # S1L12) # !D1_W_alu_result[4] & D1_F_pc[2] & !S1L12;
S1_tri_state_bridge_0_address[4] = DFFEA(S1_tri_state_bridge_0_address[4]_lut_out, clk, B1_d2_reset_n, , , , );


--S1_tri_state_bridge_0_address[3] is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[3]
--operation mode is normal

S1_tri_state_bridge_0_address[3]_lut_out = D1_W_alu_result[3] & (D1_F_pc[1] # S1L12) # !D1_W_alu_result[3] & D1_F_pc[1] & !S1L12;
S1_tri_state_bridge_0_address[3] = DFFEA(S1_tri_state_bridge_0_address[3]_lut_out, clk, B1_d2_reset_n, , , , );


--S1_tri_state_bridge_0_address[2] is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[2]
--operation mode is normal

S1_tri_state_bridge_0_address[2]_lut_out = D1_W_alu_result[2] & (D1_F_pc[0] # S1L12) # !D1_W_alu_result[2] & D1_F_pc[0] & !S1L12;
S1_tri_state_bridge_0_address[2] = DFFEA(S1_tri_state_bridge_0_address[2]_lut_out, clk, B1_d2_reset_n, , , , );


--S1_tri_state_bridge_0_address[1] is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[1]
--operation mode is normal

S1_tri_state_bridge_0_address[1]_lut_out = E1_cpu_0_data_master_dbs_address[1] & (F1_cpu_0_instruction_master_dbs_address[1] # S1L12) # !E1_cpu_0_data_master_dbs_address[1] & F1_cpu_0_instruction_master_dbs_address[1] & !S1L12;
S1_tri_state_bridge_0_address[1] = DFFEA(S1_tri_state_bridge_0_address[1]_lut_out, clk, B1_d2_reset_n, , , , );


--A1L6 is altera_internal_jtag~TDO
A1L6 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1L31Q);

--A1L7 is altera_internal_jtag~TMSUTAP
A1L7 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1L31Q);

--A1L5 is altera_internal_jtag~TCKUTAP
A1L5 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1L31Q);

--altera_internal_jtag is altera_internal_jtag
altera_internal_jtag = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1L31Q);


--W1_d_write is UP3_Board:inst|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench|d_write
--operation mode is normal

W1_d_write = AMPP_FUNCTION(clk, D1_d_write_nxt, B1_d2_reset_n);


--D1_W_alu_result[21] is UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[21]
--operation mode is normal

D1_W_alu_result[21] = AMPP_FUNCTION(clk, Y1_result[21], D1L331, D1_E_shift_rot_result[21], D1_R_ctrl_dst_data_sel_logic_result, B1_d2_reset_n, D1L001, D1_R_ctrl_shift_rot);


--D1_d_read is UP3_Board:inst|cpu_0:the_cpu_0|d_read
--operation mode is normal

D1_d_read = AMPP_FUNCTION(clk, D1_E_new_inst, D1_R_ctrl_ld, D1_d_read, E1_cpu_0_data_master_waitrequest, B1_d2_reset_n);


--S1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1] is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1]
--operation mode is normal

S1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1]_lut_out = S1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0];
S1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1] = DFFEA(S1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1]_lut_out, clk, B1_d2_reset_n, , , , );


--S1L32 is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_0_s1~263
--operation mode is normal

S1L32 = D1_W_alu_result[21] & (D1_d_read & !S1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1] # !D1_d_read & W1_d_write);


--E1_cpu_0_data_master_no_byte_enables_and_last_term is UP3_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_no_byte_enables_and_last_term
--operation mode is normal

E1_cpu_0_data_master_no_byte_enables_and_last_term_lut_out = E1L331;
E1_cpu_0_data_master_no_byte_enables_and_last_term = DFFEA(E1_cpu_0_data_master_no_byte_enables_and_last_term_lut_out, clk, B1_d2_reset_n, , , , );


--S1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0] is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0]
--operation mode is normal

S1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0]_lut_out = S1L01 & !S1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & !S1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0] & !S1L71;
S1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0] = DFFEA(S1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0]_lut_out, clk, B1_d2_reset_n, , , , );


--S1L42 is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_0_s1~264
--operation mode is normal

S1L42 = W1_d_write & !E1_cpu_0_data_master_no_byte_enables_and_last_term & (!S1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0] # !D1_d_read) # !W1_d_write & (!S1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0] # !D1_d_read);


--D1_d_byteenable[2] is UP3_Board:inst|cpu_0:the_cpu_0|d_byteenable[2]
--operation mode is normal

D1_d_byteenable[2] = AMPP_FUNCTION(clk, D1_D_iw[4], D1_D_iw[3], Y1_result[1], Y1_result[0], B1_d2_reset_n);


--D1_d_byteenable[0] is UP3_Board:inst|cpu_0:the_cpu_0|d_byteenable[0]
--operation mode is normal

D1_d_byteenable[0] = AMPP_FUNCTION(clk, D1_D_iw[4], D1_D_iw[3], Y1_result[0], Y1_result[1], B1_d2_reset_n);


--E1_cpu_0_data_master_dbs_address[1] is UP3_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_address[1]
--operation mode is normal

E1_cpu_0_data_master_dbs_address[1]_lut_out = !E1_cpu_0_data_master_dbs_address[1];
E1_cpu_0_data_master_dbs_address[1] = DFFEA(E1_cpu_0_data_master_dbs_address[1]_lut_out, clk, B1_d2_reset_n, , E1L4, , );


--S1L81 is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_byteenable_cfi_flash_0_s1[0]~30
--operation mode is normal

S1L81 = D1_d_byteenable[2] & (D1_d_byteenable[0] # E1_cpu_0_data_master_dbs_address[1]) # !D1_d_byteenable[2] & D1_d_byteenable[0] & !E1_cpu_0_data_master_dbs_address[1];


--D1_d_byteenable[3] is UP3_Board:inst|cpu_0:the_cpu_0|d_byteenable[3]
--operation mode is normal

D1_d_byteenable[3] = AMPP_FUNCTION(clk, D1_D_iw[4], Y1_result[0], Y1_result[1], D1_D_iw[3], B1_d2_reset_n);


--D1_d_byteenable[1] is UP3_Board:inst|cpu_0:the_cpu_0|d_byteenable[1]
--operation mode is normal

D1_d_byteenable[1] = AMPP_FUNCTION(clk, D1_D_iw[4], Y1_result[0], D1_D_iw[3], Y1_result[1], B1_d2_reset_n);


--S1L91 is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_byteenable_cfi_flash_0_s1[1]~31
--operation mode is normal

S1L91 = D1_d_byteenable[3] & (D1_d_byteenable[1] # E1_cpu_0_data_master_dbs_address[1]) # !D1_d_byteenable[3] & D1_d_byteenable[1] & !E1_cpu_0_data_master_dbs_address[1];


--S1L52 is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_0_s1~265
--operation mode is normal

S1L52 = W1_d_write & !S1L81 & !S1L91;


--D1_F_pc[19] is UP3_Board:inst|cpu_0:the_cpu_0|F_pc[19]
--operation mode is normal

D1_F_pc[19] = AMPP_FUNCTION(clk, D1L964, Y1_result[21], D1L333, D1L524, B1_d2_reset_n, D1_W_valid);


--D1_i_read is UP3_Board:inst|cpu_0:the_cpu_0|i_read
--operation mode is normal

D1_i_read = AMPP_FUNCTION(clk, D1_W_valid, F1L7, F1L01, D1_i_read, B1_d2_reset_n);