--S1L63 is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_requests_cfi_flash_0_s1~146
--operation mode is normal

S1L63 = D1_F_pc[19] & !D1_i_read;


--S1_d1_reasons_to_wait is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_reasons_to_wait
--operation mode is normal

S1_d1_reasons_to_wait_lut_out = S1L99 & (S1L11 # S1_cfi_flash_0_s1_in_a_read_cycle) # !S1L99 & S1L67 & (S1L11 # S1_cfi_flash_0_s1_in_a_read_cycle);
S1_d1_reasons_to_wait = DFFEA(S1_d1_reasons_to_wait_lut_out, clk, B1_d2_reset_n, , , , );


--S1_cpu_0_data_master_s_turn_at_cfi_flash_0_s1 is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_s_turn_at_cfi_flash_0_s1
--operation mode is normal

S1_cpu_0_data_master_s_turn_at_cfi_flash_0_s1_lut_out = !S1_grant_0;
S1_cpu_0_data_master_s_turn_at_cfi_flash_0_s1 = DFFEA(S1_cpu_0_data_master_s_turn_at_cfi_flash_0_s1_lut_out, clk, B1_d2_reset_n, , , , );


--S1_d1_cpu_0_data_master_granted_cfi_flash_0_s1 is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_cpu_0_data_master_granted_cfi_flash_0_s1
--operation mode is normal

S1_d1_cpu_0_data_master_granted_cfi_flash_0_s1_lut_out = S1L12;
S1_d1_cpu_0_data_master_granted_cfi_flash_0_s1 = DFFEA(S1_d1_cpu_0_data_master_granted_cfi_flash_0_s1_lut_out, clk, B1_d2_reset_n, , , , );


--E1L041 is UP3_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|r_0~564
--operation mode is normal

E1L041 = S1_d1_reasons_to_wait & !S1_d1_cpu_0_data_master_granted_cfi_flash_0_s1 # !S1_d1_reasons_to_wait & !S1_cpu_0_data_master_s_turn_at_cfi_flash_0_s1;


--S1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1]
--operation mode is normal

S1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1]_lut_out = S1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0];
S1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] = DFFEA(S1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1]_lut_out, clk, B1_d2_reset_n, , , , );


--S1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0] is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0]
--operation mode is normal

S1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0]_lut_out = !S1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & !S1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0] & S1L13 & !S1L71;
S1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0] = DFFEA(S1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0]_lut_out, clk, B1_d2_reset_n, , , , );


--S1L02 is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_granted_cfi_flash_0_s1~88
--operation mode is normal

S1L02 = S1L63 & E1L041 & !S1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & !S1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0];


--S1L12 is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_granted_cfi_flash_0_s1~89
--operation mode is normal

S1L12 = S1L32 & S1L42 & !S1L52 & !S1L02;


--S1L11 is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_in_a_write_cycle~21
--operation mode is normal

S1L11 = W1_d_write & S1L12;


--S1_cfi_flash_0_s1_wait_counter[3] is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_wait_counter[3]
--operation mode is normal

S1_cfi_flash_0_s1_wait_counter[3]_lut_out = S1L8 # S1_cfi_flash_0_s1_wait_counter[3] & (S1_cfi_flash_0_s1_wait_counter[2] # !S1L2);
S1_cfi_flash_0_s1_wait_counter[3] = DFFEA(S1_cfi_flash_0_s1_wait_counter[3]_lut_out, clk, B1_d2_reset_n, , , , );


--S1_cfi_flash_0_s1_wait_counter[1] is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_wait_counter[1]
--operation mode is normal

S1_cfi_flash_0_s1_wait_counter[1]_lut_out = !S1L8 & (S1_cfi_flash_0_s1_wait_counter[1] & S1_cfi_flash_0_s1_wait_counter[0] # !S1_cfi_flash_0_s1_wait_counter[1] & !S1_cfi_flash_0_s1_wait_counter[0] & !E1L341);
S1_cfi_flash_0_s1_wait_counter[1] = DFFEA(S1_cfi_flash_0_s1_wait_counter[1]_lut_out, clk, B1_d2_reset_n, , , , );


--S1_cfi_flash_0_s1_wait_counter[0] is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_wait_counter[0]
--operation mode is normal

S1_cfi_flash_0_s1_wait_counter[0]_lut_out = S1_cfi_flash_0_s1_in_a_read_cycle & (S1L5 # S1L99) # !S1_cfi_flash_0_s1_in_a_read_cycle & S1L5 & (!S1L11 # !S1L99);
S1_cfi_flash_0_s1_wait_counter[0] = DFFEA(S1_cfi_flash_0_s1_wait_counter[0]_lut_out, clk, B1_d2_reset_n, , , , );


--S1_cfi_flash_0_s1_wait_counter[2] is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_wait_counter[2]
--operation mode is normal

S1_cfi_flash_0_s1_wait_counter[2]_lut_out = S1L6 & (!S1_cfi_flash_0_s1_in_a_read_cycle # !S1L99) # !S1L6 & S1L11 & S1L99 & !S1_cfi_flash_0_s1_in_a_read_cycle;
S1_cfi_flash_0_s1_wait_counter[2] = DFFEA(S1_cfi_flash_0_s1_wait_counter[2]_lut_out, clk, B1_d2_reset_n, , , , );


--S1L1 is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|LessThan~102
--operation mode is normal

S1L1 = !S1_cfi_flash_0_s1_wait_counter[2] & (!S1_cfi_flash_0_s1_wait_counter[0] # !S1_cfi_flash_0_s1_wait_counter[1]);


--S1_cpu_0_data_master_qualified_request_cfi_flash_0_s1 is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_0_s1
--operation mode is normal

S1_cpu_0_data_master_qualified_request_cfi_flash_0_s1 = S1L32 & S1L42 & !S1L52;


--S1L53 is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register_in~27
--operation mode is normal

S1L53 = !S1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & !S1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0];


--S1L99 is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_begins_xfer~181
--operation mode is normal

S1L99 = !S1_d1_reasons_to_wait & (S1_cpu_0_data_master_qualified_request_cfi_flash_0_s1 # S1L63 & S1L53);


--B1_d2_reset_n is UP3_Board:inst|d2_reset_n
--operation mode is normal

B1_d2_reset_n_lut_out = B1_d1_reset_n_sources;
B1_d2_reset_n = DFFEA(B1_d2_reset_n_lut_out, clk, VCC, , , , );


--S1_d1_cpu_0_instruction_master_granted_cfi_flash_0_s1 is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_cpu_0_instruction_master_granted_cfi_flash_0_s1
--operation mode is normal

S1_d1_cpu_0_instruction_master_granted_cfi_flash_0_s1_lut_out = S1L13;
S1_d1_cpu_0_instruction_master_granted_cfi_flash_0_s1 = DFFEA(S1_d1_cpu_0_instruction_master_granted_cfi_flash_0_s1_lut_out, clk, B1_d2_reset_n, , , , );


--F1L82 is UP3_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|r_0~212
--operation mode is normal

F1L82 = S1_cpu_0_data_master_s_turn_at_cfi_flash_0_s1 & (!S1_d1_cpu_0_instruction_master_granted_cfi_flash_0_s1 # !S1_d1_reasons_to_wait) # !S1_cpu_0_data_master_s_turn_at_cfi_flash_0_s1 & S1_d1_reasons_to_wait & !S1_d1_cpu_0_instruction_master_granted_cfi_flash_0_s1;


--S1L13 is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_granted_cfi_flash_0_s1~167
--operation mode is normal

S1L13 = S1L63 & S1L53 & (!F1L82 # !S1_cpu_0_data_master_qualified_request_cfi_flash_0_s1);


--S1L01 is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_in_a_read_cycle~26
--operation mode is normal

S1L01 = D1_d_read & S1L12;


--D1_W_alu_result[20] is UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[20]
--operation mode is normal

D1_W_alu_result[20] = AMPP_FUNCTION(clk, Y1_result[20], D1L231, D1_E_shift_rot_result[20], D1_R_ctrl_dst_data_sel_logic_result, B1_d2_reset_n, D1L001, D1_R_ctrl_shift_rot);


--D1_F_pc[18] is UP3_Board:inst|cpu_0:the_cpu_0|F_pc[18]
--operation mode is normal

D1_F_pc[18] = AMPP_FUNCTION(clk, D1L764, Y1_result[20], D1L333, D1L524, B1_d2_reset_n, D1_W_valid);


--D1_W_alu_result[19] is UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[19]
--operation mode is normal

D1_W_alu_result[19] = AMPP_FUNCTION(clk, Y1_result[19], D1L131, D1_E_shift_rot_result[19], D1_R_ctrl_dst_data_sel_logic_result, B1_d2_reset_n, D1L001, D1_R_ctrl_shift_rot);


--D1_F_pc[17] is UP3_Board:inst|cpu_0:the_cpu_0|F_pc[17]
--operation mode is normal

D1_F_pc[17] = AMPP_FUNCTION(clk, D1L564, Y1_result[19], D1L333, D1L524, B1_d2_reset_n, D1_W_valid);


--D1_W_alu_result[18] is UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[18]
--operation mode is normal

D1_W_alu_result[18] = AMPP_FUNCTION(clk, Y1_result[18], D1L031, D1_E_shift_rot_result[18], D1_R_ctrl_dst_data_sel_logic_result, B1_d2_reset_n, D1L001, D1_R_ctrl_shift_rot);


--D1_F_pc[16] is UP3_Board:inst|cpu_0:the_cpu_0|F_pc[16]
--operation mode is normal

D1_F_pc[16] = AMPP_FUNCTION(clk, D1L364, Y1_result[18], D1L333, D1L524, B1_d2_reset_n, D1_W_valid);


--D1_W_alu_result[17] is UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[17]
--operation mode is normal

D1_W_alu_result[17] = AMPP_FUNCTION(clk, Y1_result[17], D1L921, D1_E_shift_rot_result[17], D1_R_ctrl_dst_data_sel_logic_result, B1_d2_reset_n, D1L001, D1_R_ctrl_shift_rot);


--D1_F_pc[15] is UP3_Board:inst|cpu_0:the_cpu_0|F_pc[15]
--operation mode is normal

D1_F_pc[15] = AMPP_FUNCTION(clk, D1L164, Y1_result[17], D1L333, D1L524, B1_d2_reset_n, D1_W_valid);


--D1_W_alu_result[16] is UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[16]
--operation mode is normal

D1_W_alu_result[16] = AMPP_FUNCTION(clk, Y1_result[16], D1L821, D1_E_shift_rot_result[16], D1_R_ctrl_dst_data_sel_logic_result, B1_d2_reset_n, D1L001, D1_R_ctrl_shift_rot);


--D1_F_pc[14] is UP3_Board:inst|cpu_0:the_cpu_0|F_pc[14]
--operation mode is normal

D1_F_pc[14] = AMPP_FUNCTION(clk, D1L954, Y1_result[16], D1L333, D1L524, B1_d2_reset_n, D1_W_valid);


--D1_W_alu_result[15] is UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[15]
--operation mode is normal

D1_W_alu_result[15] = AMPP_FUNCTION(clk, Y1_result[15], D1L721, D1_E_shift_rot_result[15], D1_R_ctrl_dst_data_sel_logic_result, B1_d2_reset_n, D1L001, D1_R_ctrl_shift_rot);


--D1_F_pc[13] is UP3_Board:inst|cpu_0:the_cpu_0|F_pc[13]
--operation mode is normal

D1_F_pc[13] = AMPP_FUNCTION(clk, D1L754, Y1_result[15], D1L333, D1L524, B1_d2_reset_n, D1_W_valid);


--D1_W_alu_result[14] is UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[14]
--operation mode is normal

D1_W_alu_result[14] = AMPP_FUNCTION(clk, Y1_result[14], D1L621, D1_E_shift_rot_result[14], D1_R_ctrl_dst_data_sel_logic_result, B1_d2_reset_n, D1L001, D1_R_ctrl_shift_rot);


--D1_F_pc[12] is UP3_Board:inst|cpu_0:the_cpu_0|F_pc[12]
--operation mode is normal

D1_F_pc[12] = AMPP_FUNCTION(clk, D1L554, Y1_result[14], D1L333, D1L524, B1_d2_reset_n, D1_W_valid);


--D1_W_alu_result[13] is UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[13]
--operation mode is normal

D1_W_alu_result[13] = AMPP_FUNCTION(clk, Y1_result[13], D1L521, D1_E_shift_rot_result[13], D1_R_ctrl_dst_data_sel_logic_result, B1_d2_reset_n, D1L001, D1_R_ctrl_shift_rot);


--D1_F_pc[11] is UP3_Board:inst|cpu_0:the_cpu_0|F_pc[11]
--operation mode is normal

D1_F_pc[11] = AMPP_FUNCTION(clk, D1L354, Y1_result[13], D1L333, D1L524, B1_d2_reset_n, D1_W_valid);


--D1_W_alu_result[12] is UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[12]
--operation mode is normal

D1_W_alu_result[12] = AMPP_FUNCTION(clk, Y1_result[12], D1L421, D1_E_shift_rot_result[12], D1_R_ctrl_dst_data_sel_logic_result, B1_d2_reset_n, D1L001, D1_R_ctrl_shift_rot);


--D1_F_pc[10] is UP3_Board:inst|cpu_0:the_cpu_0|F_pc[10]
--operation mode is normal

D1_F_pc[10] = AMPP_FUNCTION(clk, D1L154, Y1_result[12], D1L333, D1L524, B1_d2_reset_n, D1_W_valid);


--D1_W_alu_result[11] is UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[11]
--operation mode is normal

D1_W_alu_result[11] = AMPP_FUNCTION(clk, Y1_result[11], D1L321, D1_E_shift_rot_result[11], D1_R_ctrl_dst_data_sel_logic_result, B1_d2_reset_n, D1L001, D1_R_ctrl_shift_rot);


--D1_F_pc[9] is UP3_Board:inst|cpu_0:the_cpu_0|F_pc[9]
--operation mode is normal

D1_F_pc[9] = AMPP_FUNCTION(clk, D1L944, Y1_result[11], D1L333, D1L524, B1_d2_reset_n, D1_W_valid);


--D1_W_alu_result[10] is UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[10]
--operation mode is normal

D1_W_alu_result[10] = AMPP_FUNCTION(clk, Y1_result[10], D1L221, D1_E_shift_rot_result[10], D1_R_ctrl_dst_data_sel_logic_result, B1_d2_reset_n, D1L001, D1_R_ctrl_shift_rot);


--D1_F_pc[8] is UP3_Board:inst|cpu_0:the_cpu_0|F_pc[8]
--operation mode is normal

D1_F_pc[8] = AMPP_FUNCTION(clk, D1L744, Y1_result[10], D1L333, D1L524, B1_d2_reset_n, D1_W_valid);


--D1_W_alu_result[9] is UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[9]
--operation mode is normal