D1_W_alu_result[9] = AMPP_FUNCTION(clk, Y1_result[9], D1L121, D1_E_shift_rot_result[9], D1_R_ctrl_dst_data_sel_logic_result, B1_d2_reset_n, D1L001, D1_R_ctrl_shift_rot);


--D1_F_pc[7] is UP3_Board:inst|cpu_0:the_cpu_0|F_pc[7]
--operation mode is normal

D1_F_pc[7] = AMPP_FUNCTION(clk, D1L544, Y1_result[9], D1L333, D1L524, B1_d2_reset_n, D1_W_valid);


--D1_W_alu_result[8] is UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[8]
--operation mode is normal

D1_W_alu_result[8] = AMPP_FUNCTION(clk, Y1_result[8], D1L021, D1_E_shift_rot_result[8], D1_R_ctrl_dst_data_sel_logic_result, B1_d2_reset_n, D1L001, D1_R_ctrl_shift_rot);


--D1_F_pc[6] is UP3_Board:inst|cpu_0:the_cpu_0|F_pc[6]
--operation mode is normal

D1_F_pc[6] = AMPP_FUNCTION(clk, D1L344, Y1_result[8], D1L333, D1L524, B1_d2_reset_n, D1_W_valid);


--D1_W_alu_result[7] is UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[7]
--operation mode is normal

D1_W_alu_result[7] = AMPP_FUNCTION(clk, Y1_result[7], D1L911, D1_E_shift_rot_result[7], D1_R_ctrl_dst_data_sel_logic_result, B1_d2_reset_n, D1L001, D1_R_ctrl_shift_rot);


--D1_F_pc[5] is UP3_Board:inst|cpu_0:the_cpu_0|F_pc[5]
--operation mode is normal

D1_F_pc[5] = AMPP_FUNCTION(clk, D1L144, Y1_result[7], D1L333, D1L524, B1_d2_reset_n, D1_W_valid);


--D1_W_alu_result[6] is UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[6]
--operation mode is normal

D1_W_alu_result[6] = AMPP_FUNCTION(clk, Y1_result[6], D1L811, D1_E_shift_rot_result[6], D1_R_ctrl_dst_data_sel_logic_result, B1_d2_reset_n, D1L001, D1_R_ctrl_shift_rot);


--D1_F_pc[4] is UP3_Board:inst|cpu_0:the_cpu_0|F_pc[4]
--operation mode is normal

D1_F_pc[4] = AMPP_FUNCTION(clk, D1L934, Y1_result[6], D1L333, D1L524, B1_d2_reset_n, D1_W_valid);


--D1_W_alu_result[5] is UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[5]
--operation mode is normal

D1_W_alu_result[5] = AMPP_FUNCTION(clk, Y1_result[5], D1L711, D1_E_shift_rot_result[5], D1_R_ctrl_dst_data_sel_logic_result, B1_d2_reset_n, D1L001, D1_R_ctrl_shift_rot);


--D1_F_pc[3] is UP3_Board:inst|cpu_0:the_cpu_0|F_pc[3]
--operation mode is normal

D1_F_pc[3] = AMPP_FUNCTION(clk, D1_R_ctrl_exception, D1L433, D1_R_ctrl_break, B1_d2_reset_n, D1_W_valid);


--D1_W_alu_result[4] is UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[4]
--operation mode is normal

D1_W_alu_result[4] = AMPP_FUNCTION(clk, Y1_result[4], D1L611, D1_E_shift_rot_result[4], D1_R_ctrl_dst_data_sel_logic_result, B1_d2_reset_n, D1L001, D1_R_ctrl_shift_rot);


--D1_F_pc[2] is UP3_Board:inst|cpu_0:the_cpu_0|F_pc[2]
--operation mode is normal

D1_F_pc[2] = AMPP_FUNCTION(clk, D1L534, Y1_result[4], D1L333, D1L524, B1_d2_reset_n, D1_W_valid);


--D1_W_alu_result[3] is UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[3]
--operation mode is normal

D1_W_alu_result[3] = AMPP_FUNCTION(clk, Y1_result[3], D1L511, D1_E_shift_rot_result[3], D1_R_ctrl_dst_data_sel_logic_result, B1_d2_reset_n, D1L001, D1_R_ctrl_shift_rot);


--D1_F_pc[1] is UP3_Board:inst|cpu_0:the_cpu_0|F_pc[1]
--operation mode is normal

D1_F_pc[1] = AMPP_FUNCTION(clk, D1L334, Y1_result[3], D1L333, D1L524, B1_d2_reset_n, D1_W_valid);


--D1_W_alu_result[2] is UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[2]
--operation mode is normal

D1_W_alu_result[2] = AMPP_FUNCTION(clk, Y1_result[2], D1L411, D1_E_shift_rot_result[2], D1_R_ctrl_dst_data_sel_logic_result, B1_d2_reset_n, D1L001, D1_R_ctrl_shift_rot);


--D1_F_pc[0] is UP3_Board:inst|cpu_0:the_cpu_0|F_pc[0]
--operation mode is normal

D1_F_pc[0] = AMPP_FUNCTION(clk, D1L134, Y1_result[2], D1L333, D1L524, B1_d2_reset_n, D1_W_valid);


--F1_cpu_0_instruction_master_dbs_address[1] is UP3_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_dbs_address[1]
--operation mode is normal

F1_cpu_0_instruction_master_dbs_address[1]_lut_out = !F1_cpu_0_instruction_master_dbs_address[1];
F1_cpu_0_instruction_master_dbs_address[1] = DFFEA(F1_cpu_0_instruction_master_dbs_address[1]_lut_out, clk, B1_d2_reset_n, , F1L5, , );


--C1L31Q is sld_hub:sld_hub_inst|HUB_TDO~reg0
--operation mode is normal

C1L31Q = AMPP_FUNCTION(!A1L5, UB6_Q[0], C1L11, C1L21, C1_jtag_debug_mode_usr1, !YB1_state[8], DB1L41);


--D1_E_new_inst is UP3_Board:inst|cpu_0:the_cpu_0|E_new_inst
--operation mode is normal

D1_E_new_inst = AMPP_FUNCTION(clk, D1_R_valid, B1_d2_reset_n);


--D1_R_ctrl_st is UP3_Board:inst|cpu_0:the_cpu_0|R_ctrl_st
--operation mode is normal

D1_R_ctrl_st = AMPP_FUNCTION(clk, D1_D_iw[0], D1_D_iw[1], B1_d2_reset_n);


--E1_cpu_0_data_master_waitrequest is UP3_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_waitrequest
--operation mode is normal

E1_cpu_0_data_master_waitrequest_lut_out = E1L141 & E1L301 & E1L501 & E1L011;
E1_cpu_0_data_master_waitrequest = DFFEA(E1_cpu_0_data_master_waitrequest_lut_out, clk, B1_d2_reset_n, , , , );


--D1_d_write_nxt is UP3_Board:inst|cpu_0:the_cpu_0|d_write_nxt
--operation mode is normal

D1_d_write_nxt = AMPP_FUNCTION(D1_E_new_inst, D1_R_ctrl_st, W1_d_write, E1_cpu_0_data_master_waitrequest);


--Y1_result[21] is UP3_Board:inst|cpu_0:the_cpu_0|lpm_add_sub:add_rtl_1|alt_stratix_add_sub:stratix_adder|result[21]
--operation mode is arithmetic

Y1_result[21] = AMPP_FUNCTION(D1_E_src2[21], D1_E_src1[21], Y1L34, D1_E_alu_sub);

--Y1L54 is UP3_Board:inst|cpu_0:the_cpu_0|lpm_add_sub:add_rtl_1|alt_stratix_add_sub:stratix_adder|add_sub_cell[21]~COUT
--operation mode is arithmetic

Y1L54 = AMPP_FUNCTION(D1_E_src2[21], D1_E_src1[21], Y1L34, D1_E_alu_sub);


--D1_R_logic_op[1] is UP3_Board:inst|cpu_0:the_cpu_0|R_logic_op[1]
--operation mode is normal

D1_R_logic_op[1] = AMPP_FUNCTION(clk, D1L5, D1L6, D1L2, D1L51, B1_d2_reset_n);


--D1_E_src1[21] is UP3_Board:inst|cpu_0:the_cpu_0|E_src1[21]
--operation mode is normal

D1_E_src1[21] = AMPP_FUNCTION(clk, AB1_q_a[21], D1_D_iw[25], D1L964, D1L963, B1_d2_reset_n, D1L863);


--D1_E_src2[21] is UP3_Board:inst|cpu_0:the_cpu_0|E_src2[21]
--operation mode is normal

D1_E_src2[21] = AMPP_FUNCTION(clk, AB1_q_b[21], D1_D_iw[21], D1_D_iw[11], D1_R_src2_use_imm, B1_d2_reset_n, D1L173, D1_R_ctrl_hi_imm);


--D1_R_logic_op[0] is UP3_Board:inst|cpu_0:the_cpu_0|R_logic_op[0]
--operation mode is normal

D1_R_logic_op[0] = AMPP_FUNCTION(clk, D1L5, D1L6, D1L1, D1L51, B1_d2_reset_n);


--D1L331 is UP3_Board:inst|cpu_0:the_cpu_0|E_logic_result[21]~10527
--operation mode is normal

D1L331 = AMPP_FUNCTION(D1_R_logic_op[1], D1_E_src1[21], D1_E_src2[21], D1_R_logic_op[0]);


--D1_E_shift_rot_result[21] is UP3_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[21]
--operation mode is normal

D1_E_shift_rot_result[21] = AMPP_FUNCTION(clk, D1_E_shift_rot_result[20], D1_E_shift_rot_result[22], D1_E_src1[21], D1_R_ctrl_shift_rot_right, B1_d2_reset_n, D1_E_new_inst);


--D1_R_ctrl_dst_data_sel_logic_result is UP3_Board:inst|cpu_0:the_cpu_0|R_ctrl_dst_data_sel_logic_result
--operation mode is normal

D1_R_ctrl_dst_data_sel_logic_result = AMPP_FUNCTION(clk, D1L81, D1L19, D1L29, D1_D_iw[16], B1_d2_reset_n);


--D1_R_ctrl_dst_data_sel_cmp is UP3_Board:inst|cpu_0:the_cpu_0|R_ctrl_dst_data_sel_cmp
--operation mode is normal

D1_R_ctrl_dst_data_sel_cmp = AMPP_FUNCTION(clk, D1L61, D1_D_iw[0], D1L71, D1L41, B1_d2_reset_n);


--D1_R_ctrl_rdctl_inst is UP3_Board:inst|cpu_0:the_cpu_0|R_ctrl_rdctl_inst
--operation mode is normal

D1_R_ctrl_rdctl_inst = AMPP_FUNCTION(clk, D1_D_iw[16], D1L19, D1L78, D1L29, B1_d2_reset_n);


--D1L001 is UP3_Board:inst|cpu_0:the_cpu_0|E_alu_result~0
--operation mode is normal

D1L001 = AMPP_FUNCTION(D1_R_ctrl_dst_data_sel_cmp, D1_R_ctrl_rdctl_inst);


--D1_R_ctrl_shift_rot is UP3_Board:inst|cpu_0:the_cpu_0|R_ctrl_shift_rot
--operation mode is normal

D1_R_ctrl_shift_rot = AMPP_FUNCTION(clk, D1L72, B1_d2_reset_n);


--D1_R_ctrl_ld is UP3_Board:inst|cpu_0:the_cpu_0|R_ctrl_ld
--operation mode is normal

D1_R_ctrl_ld = AMPP_FUNCTION(clk, D1_D_iw[1], D1_D_iw[0], D1_D_iw[2], D1_D_iw[4], B1_d2_reset_n);


--E1L331 is UP3_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|last_dbs_term_and_run~31
--operation mode is normal

E1L331 = W1_d_write & E1_cpu_0_data_master_dbs_address[1] & !D1_d_byteenable[2] & !D1_d_byteenable[3];


--S1L67 is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|reduce_nor~2
--operation mode is normal

S1L67 = S1_cfi_flash_0_s1_wait_counter[3] # S1_cfi_flash_0_s1_wait_counter[2] # S1_cfi_flash_0_s1_wait_counter[1] # S1_cfi_flash_0_s1_wait_counter[0];


--S1L71 is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_waits_for_read~102
--operation mode is normal

S1L71 = S1L99 & (S1L13 # S1L01) # !S1L99 & S1L67 & (S1L13 # S1L01);


--D1_D_iw[4] is UP3_Board:inst|cpu_0:the_cpu_0|D_iw[4]
--operation mode is normal

D1_D_iw[4] = AMPP_FUNCTION(clk, D1_intr_req, D1L662, F1_dbs_16_reg_segment_0[4], D1L762, B1_d2_reset_n, D1_F_valid);


--D1_D_iw[3] is UP3_Board:inst|cpu_0:the_cpu_0|D_iw[3]
--operation mode is normal

D1_D_iw[3] = AMPP_FUNCTION(clk, D1_intr_req, D1L562, D1L762, F1_dbs_16_reg_segment_0[3], B1_d2_reset_n, D1_F_valid);


--Y1_result[1] is UP3_Board:inst|cpu_0:the_cpu_0|lpm_add_sub:add_rtl_1|alt_stratix_add_sub:stratix_adder|result[1]
--operation mode is arithmetic

Y1_result[1] = AMPP_FUNCTION(D1_E_src2[1], D1_E_src1[1], Y1L3, D1_E_alu_sub);

--Y1L5 is UP3_Board:inst|cpu_0:the_cpu_0|lpm_add_sub:add_rtl_1|alt_stratix_add_sub:stratix_adder|add_sub_cell[1]~COUT
--operation mode is arithmetic

Y1L5 = AMPP_FUNCTION(D1_E_src2[1], D1_E_src1[1], Y1L3, D1_E_alu_sub);


--Y1_result[0] is UP3_Board:inst|cpu_0:the_cpu_0|lpm_add_sub:add_rtl_1|alt_stratix_add_sub:stratix_adder|result[0]
--operation mode is arithmetic

Y1_result[0] = AMPP_FUNCTION(D1_E_src2[0], D1_E_src1[0]);

--Y1L3 is UP3_Board:inst|cpu_0:the_cpu_0|lpm_add_sub:add_rtl_1|alt_stratix_add_sub:stratix_adder|add_sub_cell[0]~COUT
--operation mode is arithmetic

Y1L3 = AMPP_FUNCTION(D1_E_src2[0], D1_E_src1[0], D1_E_alu_sub);


--P1_cpu_0_data_master_read_data_valid_payload_buffer_s1_shift_register is UP3_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_data_master_read_data_valid_payload_buffer_s1_shift_register
--operation mode is normal

P1_cpu_0_data_master_read_data_valid_payload_buffer_s1_shift_register_lut_out = D1_d_read & P1_cpu_0_data_master_requests_payload_buffer_s1 & P1L6 & P1L2;
P1_cpu_0_data_master_read_data_valid_payload_buffer_s1_shift_register = DFFEA(P1_cpu_0_data_master_read_data_valid_payload_buffer_s1_shift_register_lut_out, clk, B1_d2_reset_n, , , , );


--S1_cpu_0_data_master_requests_cfi_flash_0_s1 is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_requests_cfi_flash_0_s1
--operation mode is normal

S1_cpu_0_data_master_requests_cfi_flash_0_s1 = D1_W_alu_result[21] & (W1_d_write # D1_d_read);


--R1L2 is UP3_Board:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_0_data_master_qualified_request_sysid_control_slave~154
--operation mode is normal

R1L2 = !D1_W_alu_result[21] & !D1_W_alu_result[20] & (W1_d_write # D1_d_read);