--R1L3 is UP3_Board:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_0_data_master_qualified_request_sysid_control_slave~155
--operation mode is normal

R1L3 = !D1_W_alu_result[19] & !D1_W_alu_result[15] & !D1_W_alu_result[14] & !D1_W_alu_result[13];


--R1L4 is UP3_Board:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_0_data_master_qualified_request_sysid_control_slave~156
--operation mode is normal

R1L4 = R1L2 & R1L3 & !D1_W_alu_result[12];


--P1_cpu_0_data_master_requests_payload_buffer_s1 is UP3_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_data_master_requests_payload_buffer_s1
--operation mode is normal

P1_cpu_0_data_master_requests_payload_buffer_s1 = D1_W_alu_result[17] & R1L4 & !D1_W_alu_result[18] & !D1_W_alu_result[16];


--E1L821 is UP3_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~332
--operation mode is normal

E1L821 = S1L52 & !E1_cpu_0_data_master_no_byte_enables_and_last_term & (S1_cpu_0_data_master_requests_cfi_flash_0_s1 # P1_cpu_0_data_master_requests_payload_buffer_s1);


--P1L3 is UP3_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_data_master_qualified_request_payload_buffer_s1~206
--operation mode is normal

P1L3 = !P1_cpu_0_data_master_read_data_valid_payload_buffer_s1_shift_register # !D1_d_read;


--P1L4 is UP3_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_data_master_qualified_request_payload_buffer_s1~207
--operation mode is normal

P1L4 = E1_cpu_0_data_master_no_byte_enables_and_last_term # E1_cpu_0_data_master_waitrequest # !S1L81 & !S1L91;


--P1L5 is UP3_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_data_master_qualified_request_payload_buffer_s1~208
--operation mode is normal

P1L5 = P1_cpu_0_data_master_requests_payload_buffer_s1 & P1L3 & (!P1L4 # !W1_d_write);


--P1_cpu_0_data_master_s_turn_at_payload_buffer_s1 is UP3_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_data_master_s_turn_at_payload_buffer_s1
--operation mode is normal

P1_cpu_0_data_master_s_turn_at_payload_buffer_s1_lut_out = !P1_grant_0;
P1_cpu_0_data_master_s_turn_at_payload_buffer_s1 = DFFEA(P1_cpu_0_data_master_s_turn_at_payload_buffer_s1_lut_out, clk, B1_d2_reset_n, , , , );


--P1_cpu_0_instruction_master_read_data_valid_payload_buffer_s1_shift_register is UP3_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_instruction_master_read_data_valid_payload_buffer_s1_shift_register
--operation mode is normal

P1_cpu_0_instruction_master_read_data_valid_payload_buffer_s1_shift_register_lut_out = P1L21 & !P1_cpu_0_instruction_master_read_data_valid_payload_buffer_s1_shift_register & (!P1L5 # !P1_cpu_0_data_master_s_turn_at_payload_buffer_s1);
P1_cpu_0_instruction_master_read_data_valid_payload_buffer_s1_shift_register = DFFEA(P1_cpu_0_instruction_master_read_data_valid_payload_buffer_s1_shift_register_lut_out, clk, B1_d2_reset_n, , , , );


--P1L52 is UP3_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|reduce_nor~60
--operation mode is normal

P1L52 = !D1_F_pc[19] & !D1_F_pc[18] & !D1_F_pc[17] & !D1_F_pc[16];


--P1L62 is UP3_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|reduce_nor~61
--operation mode is normal

P1L62 = !D1_F_pc[13] & !D1_F_pc[12] & !D1_F_pc[11] & !D1_F_pc[10];


--P1L72 is UP3_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|reduce_nor~62
--operation mode is normal

P1L72 = D1_F_pc[15] & P1L52 & P1L62 & !D1_F_pc[14];


--P1L2 is UP3_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_data_master_granted_payload_buffer_s1~33
--operation mode is normal

P1L2 = D1_i_read # P1_cpu_0_data_master_s_turn_at_payload_buffer_s1 # P1_cpu_0_instruction_master_read_data_valid_payload_buffer_s1_shift_register # !P1L72;


--E1L921 is UP3_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~333
--operation mode is normal

E1L921 = E1L821 # W1_d_write & P1L5 & P1L2;


--E1L031 is UP3_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~334
--operation mode is normal

E1L031 = S1_d1_reasons_to_wait & W1_d_write & S1L12 & !S1L67;


--E1L131 is UP3_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~335
--operation mode is normal

E1L131 = S1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1] # P1_cpu_0_data_master_read_data_valid_payload_buffer_s1_shift_register # E1L921 # E1L031;


--E1L231 is UP3_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~336
--operation mode is normal

E1L231 = W1_d_write & E1_cpu_0_data_master_waitrequest;


--E1L4 is UP3_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_address[1]~36
--operation mode is normal

E1L4 = E1L131 & (P1_cpu_0_data_master_requests_payload_buffer_s1 & !E1L231 # !P1_cpu_0_data_master_requests_payload_buffer_s1 & S1_cpu_0_data_master_requests_cfi_flash_0_s1);


--D1L964 is UP3_Board:inst|cpu_0:the_cpu_0|add~201
--operation mode is normal

D1L964 = AMPP_FUNCTION(D1_F_pc[19], D1L864);


--D1_R_ctrl_break is UP3_Board:inst|cpu_0:the_cpu_0|R_ctrl_break
--operation mode is normal

D1_R_ctrl_break = AMPP_FUNCTION(clk, D1L28, D1_D_iw[15], D1_D_iw[14], B1_d2_reset_n);


--D1_R_ctrl_br is UP3_Board:inst|cpu_0:the_cpu_0|R_ctrl_br
--operation mode is normal

D1_R_ctrl_br = AMPP_FUNCTION(clk, D1L27, B1_d2_reset_n);


--D1_W_cmp_result is UP3_Board:inst|cpu_0:the_cpu_0|W_cmp_result
--operation mode is normal

D1_W_cmp_result = AMPP_FUNCTION(clk, D1_E_logic_result_is_0, D1_R_compare_op[1], Y1_result[32], D1_R_compare_op[0], B1_d2_reset_n);


--D1L233 is UP3_Board:inst|cpu_0:the_cpu_0|F_pc_sel_nxt[0]~39
--operation mode is normal

D1L233 = AMPP_FUNCTION(D1_R_ctrl_br, D1_W_cmp_result);


--D1_R_ctrl_uncond_cti is UP3_Board:inst|cpu_0:the_cpu_0|R_ctrl_uncond_cti
--operation mode is normal

D1_R_ctrl_uncond_cti = AMPP_FUNCTION(clk, D1L39, D1L98, D1L91, D1L82, B1_d2_reset_n);


--D1_R_ctrl_exception is UP3_Board:inst|cpu_0:the_cpu_0|R_ctrl_exception
--operation mode is normal

D1_R_ctrl_exception = AMPP_FUNCTION(clk, D1_D_iw[14], D1L28, D1L12, D1L32, B1_d2_reset_n);


--D1L333 is UP3_Board:inst|cpu_0:the_cpu_0|F_pc_sel_nxt[0]~40
--operation mode is normal

D1L333 = AMPP_FUNCTION(D1_R_ctrl_break, D1L233, D1_R_ctrl_uncond_cti, D1_R_ctrl_exception);


--D1L524 is UP3_Board:inst|cpu_0:the_cpu_0|W_status_reg_pie_inst_nxt~0
--operation mode is normal

D1L524 = AMPP_FUNCTION(D1_R_ctrl_exception, D1_R_ctrl_break);


--D1_W_valid is UP3_Board:inst|cpu_0:the_cpu_0|W_valid
--operation mode is normal

D1_W_valid = AMPP_FUNCTION(clk, D1_E_valid, D1_E_new_inst, D1_R_ctrl_ld, D1L952, B1_d2_reset_n);


--H1_cpu_0_data_master_s_turn_at_data_RAM_s1 is UP3_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|cpu_0_data_master_s_turn_at_data_RAM_s1
--operation mode is normal

H1_cpu_0_data_master_s_turn_at_data_RAM_s1_lut_out = !H1_grant_0;
H1_cpu_0_data_master_s_turn_at_data_RAM_s1 = DFFEA(H1_cpu_0_data_master_s_turn_at_data_RAM_s1_lut_out, clk, B1_d2_reset_n, , , , );


--H1L01 is UP3_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|cpu_0_instruction_master_requests_data_RAM_s1~262
--operation mode is normal

H1L01 = D1_F_pc[14] & !D1_i_read & !D1_F_pc[15] & !D1_F_pc[9];


--H1L11 is UP3_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|cpu_0_instruction_master_requests_data_RAM_s1~263
--operation mode is normal

H1L11 = P1L52 & P1L62 & H1L01 & !D1_F_pc[8];


--H1_cpu_0_instruction_master_read_data_valid_data_RAM_s1_shift_register is UP3_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|cpu_0_instruction_master_read_data_valid_data_RAM_s1_shift_register
--operation mode is normal

H1_cpu_0_instruction_master_read_data_valid_data_RAM_s1_shift_register_lut_out = F1L92 & (!H1L3 # !H1_cpu_0_data_master_requests_data_RAM_s1 # !H1_cpu_0_data_master_s_turn_at_data_RAM_s1);
H1_cpu_0_instruction_master_read_data_valid_data_RAM_s1_shift_register = DFFEA(H1_cpu_0_instruction_master_read_data_valid_data_RAM_s1_shift_register_lut_out, clk, B1_d2_reset_n, , , , );


--F1L92 is UP3_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|r_0~213
--operation mode is normal

F1L92 = H1L11 & (D1_i_read # !H1_cpu_0_instruction_master_read_data_valid_data_RAM_s1_shift_register);


--R1L5 is UP3_Board:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_0_data_master_qualified_request_sysid_control_slave~157
--operation mode is normal

R1L5 = !D1_W_alu_result[11] & !D1_W_alu_result[10];


--R1L6 is UP3_Board:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_0_data_master_qualified_request_sysid_control_slave~158
--operation mode is normal

R1L6 = R1L2 & R1L3 & R1L5 & !D1_W_alu_result[12];


--H1_cpu_0_data_master_requests_data_RAM_s1 is UP3_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|cpu_0_data_master_requests_data_RAM_s1
--operation mode is normal

H1_cpu_0_data_master_requests_data_RAM_s1 = D1_W_alu_result[16] & R1L6 & !D1_W_alu_result[18] & !D1_W_alu_result[17];


--H1_cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register is UP3_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register
--operation mode is normal

H1_cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register_lut_out = D1_d_read & H1_cpu_0_data_master_requests_data_RAM_s1 & H1L3 & H1L2;
H1_cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register = DFFEA(H1_cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register_lut_out, clk, B1_d2_reset_n, , , , );


--H1L3 is UP3_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|cpu_0_data_master_qualified_request_data_RAM_s1~101
--operation mode is normal

H1L3 = W1_d_write & !E1_cpu_0_data_master_waitrequest & (!H1_cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register # !D1_d_read) # !W1_d_write & (!H1_cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register # !D1_d_read);


--H1L1 is UP3_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|always2~36
--operation mode is normal

H1L1 = F1L92 & H1_cpu_0_data_master_requests_data_RAM_s1 & H1L3;


--F1L7 is UP3_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_waitrequest~68
--operation mode is normal

F1L7 = F1L82 & !S1L4 & (!H1L1 # !H1_cpu_0_data_master_s_turn_at_data_RAM_s1) # !F1L82 & (!H1L1 # !H1_cpu_0_data_master_s_turn_at_data_RAM_s1);


--F1L8 is UP3_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_waitrequest~69
--operation mode is normal

F1L8 = D1_i_read # F1_cpu_0_instruction_master_dbs_address[1] & P1_cpu_0_instruction_master_read_data_valid_payload_buffer_s1_shift_register # !P1L72;


--H1L21 is UP3_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|cpu_0_instruction_master_requests_data_RAM_s1~264
--operation mode is normal

H1L21 = !D1_i_read & !D1_F_pc[15];


--F1L03 is UP3_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|r_0~214
--operation mode is normal

F1L03 = P1L52 & P1L62 & H1L21 & !D1_F_pc[14];


--K1_cpu_0_instruction_master_read_data_valid_firmware_ROM_s1_shift_register is UP3_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|cpu_0_instruction_master_read_data_valid_firmware_ROM_s1_shift_register
--operation mode is normal

K1_cpu_0_instruction_master_read_data_valid_firmware_ROM_s1_shift_register_lut_out = F1L13 & (!K1L3 # !K1_cpu_0_data_master_s_turn_at_firmware_ROM_s1);
K1_cpu_0_instruction_master_read_data_valid_firmware_ROM_s1_shift_register = DFFEA(K1_cpu_0_instruction_master_read_data_valid_firmware_ROM_s1_shift_register_lut_out, clk, B1_d2_reset_n, , , , );


--F1L13 is UP3_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|r_0~215
--operation mode is normal

F1L13 = F1L03 & (D1_i_read # !K1_cpu_0_instruction_master_read_data_valid_firmware_ROM_s1_shift_register);


--F1L9 is UP3_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_waitrequest~70
--operation mode is normal

F1L9 = F1L6 & !F1L92 & !F1L13;


--P1L21 is UP3_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_instruction_master_requests_payload_buffer_s1~213
--operation mode is normal