0000: 80 67    JMP   0x0068
    0002: 30       HALT  
    0003: 30       HALT  
FILE: .\boot.asm
(0001) ; Generated by PSoC Designer ver 4.2  b1013 : 02 September, 2004
(0002) ;
(0003) ;@Id: boot.tpl#15 @
(0004) ;=============================================================================
(0005) ;  FILENAME:   boot.asm
(0006) ;  VERSION:    4.15
(0007) ;  DATE:       18 August 2004
(0008) ;
(0009) ;  DESCRIPTION:
(0010) ;  M8C Boot Code for CY8C21x34 microcontroller devices.
(0011) ;
(0012) ;  Copyright (C) Cypress MicroSystems 2000-2004. All rights reserved.
(0013) ;
(0014) ; NOTES:
(0015) ; PSoC Designer's Device Editor uses a template file, BOOT.TPL, located in
(0016) ; the project's root directory to create BOOT.ASM. Any changes made to
(0017) ; BOOT.ASM will be  overwritten every time the project is generated; therfore
(0018) ; changes should be made to BOOT.TPL not BOOT.ASM. Care must be taken when
(0019) ; modifying BOOT.TPL so that replacement strings (such as @PROJECT_NAME)
(0020) ; are not accidentally modified.
(0021) ;
(0022) ;=============================================================================
(0023) 
(0024) include ".\lib\GlobalParams.inc"
(0025) include "m8c.inc"
(0026) include "m8ssc.inc"
(0027) include "memory.inc"
(0028) 
(0029) ;--------------------------------------
(0030) ; Export Declarations
(0031) ;--------------------------------------
(0032) 
(0033) export __Start
(0034) export __bss_start
(0035) export __data_start
(0036) export __idata_start
(0037) export __func_lit_start
(0038) export __text_start
(0039) export  _bGetPowerSetting
(0040) export   bGetPowerSetting
(0041) 
(0042) 
(0043) ;--------------------------------------
(0044) ; Optimization flags
(0045) ;--------------------------------------
(0046) ;
(0047) ; To change the value of these flags, modify the file boot.tpl, not
(0048) ; boot.asm. See the notes in the banner comment at the beginning of
(0049) ; this file.
(0050) 
(0051) ; Optimization for Assembly language (only) projects and C-language projects
(0052) ; that do not depend on the C compiler to initialize the values of RAM variables.
(0053) ;   Set to 1: Support for C Run-time Environment initialization
(0054) ;   Set to 0: Support for C not included. Faster start up, smaller code space.
(0055) ;
(0056) C_LANGUAGE_SUPPORT:              equ 1
(0057) 
(0058) 
(0059) ; For historical reasons, by default the boot code uses an lcall instruction
(0060) ; to invoke the user's _main code. If _main executes a return instruction,
(0061) ; boot provides an infinite loop. By changing the following equate from zero
(0062) ; to 1, boot's lcall will be replaced by a ljmp instruction, saving two
(0063) ; bytes on the stack which are otherwise required for the return address. If
(0064) ; this option is enabled, _main must not return. (Beginning with the 4.2
(0065) ; release, the C compiler automatically places an infinite loop at the end
(0066) ; of main, rather than a return instruction.)
(0067) ;
(0068) ENABLE_LJMP_TO_MAIN:             equ 0
(0069) 
(0070) 
(0071) ;-----------------------------------------------------------------------------
(0072) ; Interrupt Vector Table
(0073) ;-----------------------------------------------------------------------------
(0074) ;
(0075) ; Interrupt vector table entries are 4 bytes long.  Each one contains
(0076) ; a jump instruction to an ISR (Interrupt Service Routine), although
(0077) ; very short ISRs could be encoded within the table itself. Normally,
(0078) ; vector jump targets are modified automatically according to the user
(0079) ; modules selected. This occurs when the 'Generate Application' opera-
(0080) ; tion is run causing PSoC Designer to create boot.asm and the other
(0081) ; configuration files. If you need to hard code a vector, update the
(0082) ; file boot.tpl, not boot.asm. See the banner comment at the beginning
(0083) ; of this file.
(0084) ;-----------------------------------------------------------------------------
(0085) 
(0086)     AREA TOP (ROM, ABS, CON)
(0087) 
(0088)     org   0                        ;Reset Interrupt Vector
(0089)     jmp   __Start                  ;First instruction executed following a Reset
(0090) 
(0091)     org   04h                      ;Supply Monitor Interrupt Vector
(0092)     halt                           ;Stop execution if power falls too low
    0004: 30       HALT  
    0005: 30       HALT  
    0006: 30       HALT  
    0007: 30       HALT  
(0093) 
(0094)     org   08h                      ;Analog Column 0 Interrupt Vector
(0095)     // call	void_handler
(0096)     reti
    0008: 7E       RETI  
    0009: 30       HALT  
    000A: 30       HALT  
    000B: 30       HALT  
(0097) 
(0098)     org   0Ch                      ;Analog Column 1 Interrupt Vector
(0099)     // call	void_handler
(0100)     reti
    000C: 7E       RETI  
    000D: 30       HALT  
    000E: 30       HALT  
    000F: 30       HALT  
    0010: 30       HALT  
    0011: 30       HALT  
    0012: 30       HALT  
    0013: 30       HALT  
    0014: 30       HALT  
    0015: 30       HALT  
    0016: 30       HALT  
    0017: 30       HALT  
(0101) 
(0102)     org   18h                      ;VC3 Interrupt Vector
(0103)     // call	void_handler
(0104)     reti
    0018: 7E       RETI  
    0019: 30       HALT  
    001A: 30       HALT  
    001B: 30       HALT  
(0105) 
(0106)     org   1Ch                      ;GPIO Interrupt Vector
(0107)     // call	void_handler
(0108)     reti
    001C: 7E       RETI  
    001D: 30       HALT  
    001E: 30       HALT  
    001F: 30       HALT  
(0109) 
(0110)     org   20h                      ;PSoC Block DBB00 Interrupt Vector
(0111)     ljmp	_CSR_1_SCAN_ISR
    0020: 7D 0C F9 LJMP  _CSR_1_SCAN_ISR
(0112)     reti
    0023: 7E       RETI  
(0113) 
(0114)     org   24h                      ;PSoC Block DBB01 Interrupt Vector
(0115)     // call	void_handler
(0116)     reti
    0024: 7E       RETI  
    0025: 30       HALT  
    0026: 30       HALT  
    0027: 30       HALT  
(0117) 
(0118)     org   28h                      ;PSoC Block DCB02 Interrupt Vector
(0119)     // call	void_handler
(0120)     reti
    0028: 7E       RETI  
    0029: 30       HALT  
    002A: 30       HALT  
    002B: 30       HALT  
(0121) 
(0122)     org   2Ch                      ;PSoC Block DCB03 Interrupt Vector
(0123)     // call	void_handler
(0124)     reti
    002C: 7E       RETI  
    002D: 30       HALT  
    002E: 30       HALT  
    002F: 30       HALT  
    0030: 30       HALT  
    0031: 30       HALT  
    0032: 30       HALT  
    0033: 30       HALT  
    0034: 30       HALT  
    0035: 30       HALT  
    0036: 30       HALT  
    0037: 30       HALT  
    0038: 30       HALT  
    0039: 30       HALT  
    003A: 30       HALT  
    003B: 30       HALT  
    003C: 30       HALT  
    003D: 30       HALT  
    003E: 30       HALT  
    003F: 30       HALT  
    0040: 30       HALT  
    0041: 30       HALT  
    0042: 30       HALT  
    0043: 30       HALT  
    0044: 30       HALT  
    0045: 30       HALT  
    0046: 30       HALT  
    0047: 30       HALT  
    0048: 30       HALT  
    0049: 30       HALT  
    004A: 30       HALT  
    004B: 30       HALT  
    004C: 30       HALT  
    004D: 30       HALT  
    004E: 30       HALT  
    004F: 30       HALT  
    0050: 30       HALT  
    0051: 30       HALT  
    0052: 30       HALT  
    0053: 30       HALT  
    0054: 30       HALT  
    0055: 30       HALT  
    0056: 30       HALT  
    0057: 30       HALT  
    0058: 30       HALT  
    0059: 30       HALT  
    005A: 30       HALT  
    005B: 30       HALT  
    005C: 30       HALT  
    005D: 30       HALT  
    005E: 30       HALT  
    005F: 30       HALT  
(0125) 
(0126)     org   60h                      ;PSoC I2C Interrupt Vector
(0127)     // call	void_handler
(0128)     reti
    0060: 7E       RETI  
    0061: 30       HALT  
    0062: 30       HALT  
    0063: 30       HALT  
(0129) 
(0130)     org   64h                      ;Sleep Timer Interrupt Vector
(0131)     // call	void_handler
(0132)     reti
    0064: 7E       RETI  
    0065: 30       HALT  
    0066: 30       HALT  
    0067: 30       HALT  
(0133) 
(0134) ;-----------------------------------------------------------------------------
(0135) ;  Start of Execution.
(0136) ;-----------------------------------------------------------------------------
(0137) ;  The Supervisory ROM SWBootReset function has already completed the
(0138) ;  calibrate1 process, loading trim values for 5 volt operation.
(0139) ;
(0140)     org 68h
(0141) __Start:
(0142) 
(0143)     ; initialize SMP values for voltage stabilization, if required,
(0144)     ; leaving power-on reset (POR) level at the default (low) level, at
(0145)     ; least for now. 
(0146)     ;
(0147)     M8C_SetBank1
    0068: 71 10    OR    F,16
(0148)     mov   reg[VLT_CR], SWITCH_MODE_PUMP_JUST | LVD_TBEN_JUST | TRIP_VOLTAGE_JUST
    006A: 62 E3 87 MOV   REG[227],135
(0149)     M8C_SetBank0
    006D: 70 EF    AND   F,239
(0150) 
(0151) IF ( WATCHDOG_ENABLE )             ; WDT selected in Global Params
(0152)     M8C_EnableWatchDog
(0153) ENDIF
(0154) 
(0155)     and  reg[CPU_SCR1], ~CPU_SCR1_ECO_ALLOWED  ; Prevent ECO from being enabled
    006F: 41 FE FB AND   REG[254],251
(0156) 
(0157)     ;---------------------------
(0158)     ; Set up the Temporary stack
(0159)     ;---------------------------
(0160)     ; A temporary stack is set up for the SSC instructions.
(0161)     ; The real stack start will be assigned later.
(0162)     ;
(0163) _stack_start:          equ 80h
(0164)     mov   A, _stack_start          ; Set top of stack to end of used RAM
    0072: 50 80    MOV   A,128
(0165)     swap  SP, A                    ; This is only temporary if going to LMM
    0074: 4E       SWAP  SP,A
(0166) 
(0167)     ;------------------------
(0168)     ; Set Power-related Trim 
(0169)     ;------------------------
(0170) 
(0171) IF ( POWER_SETTING & POWER_SET_5V0)            ; *** 5.0 Volt operation   ***
(0172)  IF ( POWER_SETTING & POWER_SET_SLOW_IMO)      ; *** 6MHZ Main Oscillator ***
(0173)     or  reg[CPU_SCR1], CPU_SCR1_SLIMO
(0174)     M8SSC_Set2TableTrims 2, SSCTBL2_TRIM_IMO_5V_6MHZ, 1, SSCTBL1_TRIM_BGR_5V
(0175)  ENDIF
(0176) ENDIF ; 5.0 V Operation
(0177) 
(0178) IF ( POWER_SETTING & POWER_SET_3V3)            ; *** 3.3 Volt operation   ***
(0179)  IF ( POWER_SETTING & POWER_SET_SLOW_IMO)      ; *** 6MHZ Main Oscillator ***
(0180)     or  reg[CPU_SCR1], CPU_SCR1_SLIMO
(0181)     M8SSC_Set2TableTrims 2, SSCTBL2_TRIM_IMO_3V_6MHZ, 1, SSCTBL1_TRIM_BGR_3V
(0182)  ELSE                                          ; *** 12MHZ Main Oscillator ***
(0183)     M8SSC_SetTableTrims  1, SSCTBL1_TRIM_IMO_3V_24MHZ, SSCTBL1_TRIM_BGR_3V
(0184)  ENDIF
(0185) ENDIF ; 3.3 Volt Operation
(0186) 
(0187) IF ( POWER_SETTING & POWER_SET_2V7_12MHZ)      ; *** 2.7 Volts / 12MHZ operation ***
(0188)     or  reg[CPU_SCR1], CPU_SCR1_SLIMO
(0189)     M8SSC_SetTableTrims  2, SSCTBL2_TRIM_IMO_2V_12MHZ, SSCTBL2_TRIM_BGR_2V
(0190) ENDIF ; *** 2.7 Volts / 12MHZ operation ***
(0191) 
(0192) IF ( POWER_SETTING & POWER_SET_2V7_6MHZ)       ; *** 2.7 Volts /  6MHZ operation ***
(0193)     or  reg[CPU_SCR1], CPU_SCR1_SLIMO
(0194)     M8SSC_SetTableTrims  2, SSCTBL2_TRIM_IMO_2V_6MHZ,  SSCTBL2_TRIM_BGR_2V
(0195) ENDIF ; *** 2.7 Volts /  6MHZ operation ***
(0196) 
(0197)     mov  [bSSC_KEY1],  0           ; Lock out Flash and Supervisiory operations
    0075: 55 F8 00 MOV   [248],0
(0198)     mov  [bSSC_KEYSP], 0
    0078: 55 F9 00 MOV   [249],0
(0199) 
(0200)     ;---------------------------------------
(0201)     ; Initialize Crystal Oscillator and PLL
(0202)     ;---------------------------------------
(0203) 
(0204)     M8C_SetBank1
    007B: 71 10    OR    F,16
(0205)     mov   reg[OSC_CR0], (SLEEP_TIMER_JUST | OSC_CR0_CPU_12MHz)
    007D: 62 E0 02 MOV   REG[224],2
(0206)     M8C_SetBank0
    0080: 70 EF    AND   F,239
(0207)     M8C_ClearWDTAndSleep           ; Reset the watch dog
    0082: 62 E3 38 MOV   REG[227],56