; CSR_1SW3 address and mask equates
CSR_1SW3_Data_ADDR:	equ	0h
CSR_1SW3_DriveMode_0_ADDR:	equ	100h
CSR_1SW3_DriveMode_1_ADDR:	equ	101h
CSR_1SW3_DriveMode_2_ADDR:	equ	3h
CSR_1SW3_GlobalSelect_ADDR:	equ	2h
CSR_1SW3_IntCtrl_0_ADDR:	equ	102h
CSR_1SW3_IntCtrl_1_ADDR:	equ	103h
CSR_1SW3_IntEn_ADDR:	equ	1h
CSR_1SW3_MASK:	equ	1h
CSR_1SW3_MUXBusCtrl_ADDR:	equ	1d8h
; CSR_1SW3_Data access macros
;   GetCSR_1SW3_Data macro, return in a
macro GetCSR_1SW3_Data
	mov		a,[Port_0_Data_SHADE]
	and		a, 1h
endm
;   SetCSR_1SW3_Data macro
macro SetCSR_1SW3_Data
	or		[Port_0_Data_SHADE], 1h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm
;   SetCSR_1SW3_Data macro
macro ClearCSR_1SW3_Data
	and		[Port_0_Data_SHADE], ~1h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm

; CSR_1SW4 address and mask equates
CSR_1SW4_Data_ADDR:	equ	0h
CSR_1SW4_DriveMode_0_ADDR:	equ	100h
CSR_1SW4_DriveMode_1_ADDR:	equ	101h
CSR_1SW4_DriveMode_2_ADDR:	equ	3h
CSR_1SW4_GlobalSelect_ADDR:	equ	2h
CSR_1SW4_IntCtrl_0_ADDR:	equ	102h
CSR_1SW4_IntCtrl_1_ADDR:	equ	103h
CSR_1SW4_IntEn_ADDR:	equ	1h
CSR_1SW4_MASK:	equ	2h
CSR_1SW4_MUXBusCtrl_ADDR:	equ	1d8h
; CSR_1SW4_Data access macros
;   GetCSR_1SW4_Data macro, return in a
macro GetCSR_1SW4_Data
	mov		a,[Port_0_Data_SHADE]
	and		a, 2h
endm
;   SetCSR_1SW4_Data macro
macro SetCSR_1SW4_Data
	or		[Port_0_Data_SHADE], 2h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm
;   SetCSR_1SW4_Data macro
macro ClearCSR_1SW4_Data
	and		[Port_0_Data_SHADE], ~2h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm

; CSR_1SW5 address and mask equates
CSR_1SW5_Data_ADDR:	equ	0h
CSR_1SW5_DriveMode_0_ADDR:	equ	100h
CSR_1SW5_DriveMode_1_ADDR:	equ	101h
CSR_1SW5_DriveMode_2_ADDR:	equ	3h
CSR_1SW5_GlobalSelect_ADDR:	equ	2h
CSR_1SW5_IntCtrl_0_ADDR:	equ	102h
CSR_1SW5_IntCtrl_1_ADDR:	equ	103h
CSR_1SW5_IntEn_ADDR:	equ	1h
CSR_1SW5_MASK:	equ	4h
CSR_1SW5_MUXBusCtrl_ADDR:	equ	1d8h
; CSR_1SW5_Data access macros
;   GetCSR_1SW5_Data macro, return in a
macro GetCSR_1SW5_Data
	mov		a,[Port_0_Data_SHADE]
	and		a, 4h
endm
;   SetCSR_1SW5_Data macro
macro SetCSR_1SW5_Data
	or		[Port_0_Data_SHADE], 4h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm
;   SetCSR_1SW5_Data macro
macro ClearCSR_1SW5_Data
	and		[Port_0_Data_SHADE], ~4h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm

; CSR_1SW6 address and mask equates
CSR_1SW6_Data_ADDR:	equ	0h
CSR_1SW6_DriveMode_0_ADDR:	equ	100h
CSR_1SW6_DriveMode_1_ADDR:	equ	101h
CSR_1SW6_DriveMode_2_ADDR:	equ	3h
CSR_1SW6_GlobalSelect_ADDR:	equ	2h
CSR_1SW6_IntCtrl_0_ADDR:	equ	102h
CSR_1SW6_IntCtrl_1_ADDR:	equ	103h
CSR_1SW6_IntEn_ADDR:	equ	1h
CSR_1SW6_MASK:	equ	8h
CSR_1SW6_MUXBusCtrl_ADDR:	equ	1d8h
; CSR_1SW6_Data access macros
;   GetCSR_1SW6_Data macro, return in a
macro GetCSR_1SW6_Data
	mov		a,[Port_0_Data_SHADE]
	and		a, 8h
endm
;   SetCSR_1SW6_Data macro
macro SetCSR_1SW6_Data
	or		[Port_0_Data_SHADE], 8h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm
;   SetCSR_1SW6_Data macro
macro ClearCSR_1SW6_Data
	and		[Port_0_Data_SHADE], ~8h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm

; CSR_1SW7 address and mask equates
CSR_1SW7_Data_ADDR:	equ	0h
CSR_1SW7_DriveMode_0_ADDR:	equ	100h
CSR_1SW7_DriveMode_1_ADDR:	equ	101h
CSR_1SW7_DriveMode_2_ADDR:	equ	3h
CSR_1SW7_GlobalSelect_ADDR:	equ	2h
CSR_1SW7_IntCtrl_0_ADDR:	equ	102h
CSR_1SW7_IntCtrl_1_ADDR:	equ	103h
CSR_1SW7_IntEn_ADDR:	equ	1h
CSR_1SW7_MASK:	equ	10h
CSR_1SW7_MUXBusCtrl_ADDR:	equ	1d8h
; CSR_1SW7_Data access macros
;   GetCSR_1SW7_Data macro, return in a
macro GetCSR_1SW7_Data
	mov		a,[Port_0_Data_SHADE]
	and		a, 10h
endm
;   SetCSR_1SW7_Data macro
macro SetCSR_1SW7_Data
	or		[Port_0_Data_SHADE], 10h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm
;   SetCSR_1SW7_Data macro
macro ClearCSR_1SW7_Data
	and		[Port_0_Data_SHADE], ~10h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm

; CSR_1SW8 address and mask equates
CSR_1SW8_Data_ADDR:	equ	0h
CSR_1SW8_DriveMode_0_ADDR:	equ	100h
CSR_1SW8_DriveMode_1_ADDR:	equ	101h
CSR_1SW8_DriveMode_2_ADDR:	equ	3h
CSR_1SW8_GlobalSelect_ADDR:	equ	2h
CSR_1SW8_IntCtrl_0_ADDR:	equ	102h
CSR_1SW8_IntCtrl_1_ADDR:	equ	103h
CSR_1SW8_IntEn_ADDR:	equ	1h
CSR_1SW8_MASK:	equ	20h
CSR_1SW8_MUXBusCtrl_ADDR:	equ	1d8h
; CSR_1SW8_Data access macros
;   GetCSR_1SW8_Data macro, return in a
macro GetCSR_1SW8_Data
	mov		a,[Port_0_Data_SHADE]
	and		a, 20h
endm
;   SetCSR_1SW8_Data macro
macro SetCSR_1SW8_Data
	or		[Port_0_Data_SHADE], 20h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm
;   SetCSR_1SW8_Data macro
macro ClearCSR_1SW8_Data
	and		[Port_0_Data_SHADE], ~20h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm

; CSR_1SW9 address and mask equates
CSR_1SW9_Data_ADDR:	equ	0h
CSR_1SW9_DriveMode_0_ADDR:	equ	100h
CSR_1SW9_DriveMode_1_ADDR:	equ	101h
CSR_1SW9_DriveMode_2_ADDR:	equ	3h
CSR_1SW9_GlobalSelect_ADDR:	equ	2h
CSR_1SW9_IntCtrl_0_ADDR:	equ	102h
CSR_1SW9_IntCtrl_1_ADDR:	equ	103h
CSR_1SW9_IntEn_ADDR:	equ	1h
CSR_1SW9_MASK:	equ	40h
CSR_1SW9_MUXBusCtrl_ADDR:	equ	1d8h
; CSR_1SW9_Data access macros
;   GetCSR_1SW9_Data macro, return in a
macro GetCSR_1SW9_Data
	mov		a,[Port_0_Data_SHADE]
	and		a, 40h
endm
;   SetCSR_1SW9_Data macro
macro SetCSR_1SW9_Data
	or		[Port_0_Data_SHADE], 40h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm
;   SetCSR_1SW9_Data macro
macro ClearCSR_1SW9_Data
	and		[Port_0_Data_SHADE], ~40h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm

; CSR_1SW10 address and mask equates
CSR_1SW10_Data_ADDR:	equ	0h
CSR_1SW10_DriveMode_0_ADDR:	equ	100h
CSR_1SW10_DriveMode_1_ADDR:	equ	101h
CSR_1SW10_DriveMode_2_ADDR:	equ	3h
CSR_1SW10_GlobalSelect_ADDR:	equ	2h
CSR_1SW10_IntCtrl_0_ADDR:	equ	102h
CSR_1SW10_IntCtrl_1_ADDR:	equ	103h
CSR_1SW10_IntEn_ADDR:	equ	1h
CSR_1SW10_MASK:	equ	80h
CSR_1SW10_MUXBusCtrl_ADDR:	equ	1d8h
; CSR_1SW10_Data access macros
;   GetCSR_1SW10_Data macro, return in a
macro GetCSR_1SW10_Data
	mov		a,[Port_0_Data_SHADE]
	and		a, 80h
endm
;   SetCSR_1SW10_Data macro
macro SetCSR_1SW10_Data
	or		[Port_0_Data_SHADE], 80h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm
;   SetCSR_1SW10_Data macro
macro ClearCSR_1SW10_Data
	and		[Port_0_Data_SHADE], ~80h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm

; CSR_1SW0 address and mask equates
CSR_1SW0_Data_ADDR:	equ	4h
CSR_1SW0_DriveMode_0_ADDR:	equ	104h
CSR_1SW0_DriveMode_1_ADDR:	equ	105h
CSR_1SW0_DriveMode_2_ADDR:	equ	7h
CSR_1SW0_GlobalSelect_ADDR:	equ	6h
CSR_1SW0_IntCtrl_0_ADDR:	equ	106h
CSR_1SW0_IntCtrl_1_ADDR:	equ	107h
CSR_1SW0_IntEn_ADDR:	equ	5h
CSR_1SW0_MASK:	equ	4h
CSR_1SW0_MUXBusCtrl_ADDR:	equ	1d9h
; CSR_1SW0_Data access macros
;   GetCSR_1SW0_Data macro, return in a
macro GetCSR_1SW0_Data
	mov		a,[Port_1_Data_SHADE]
	and		a, 4h
endm
;   SetCSR_1SW0_Data macro
macro SetCSR_1SW0_Data
	or		[Port_1_Data_SHADE], 4h
	mov		reg[Port_1_Data], [Port_1_Data_SHADE]
endm
;   SetCSR_1SW0_Data macro
macro ClearCSR_1SW0_Data
	and		[Port_1_Data_SHADE], ~4h
	mov		reg[Port_1_Data], [Port_1_Data_SHADE]
endm

; CSR_1SW1 address and mask equates
CSR_1SW1_Data_ADDR:	equ	4h
CSR_1SW1_DriveMode_0_ADDR:	equ	104h
CSR_1SW1_DriveMode_1_ADDR:	equ	105h
CSR_1SW1_DriveMode_2_ADDR:	equ	7h
CSR_1SW1_GlobalSelect_ADDR:	equ	6h
CSR_1SW1_IntCtrl_0_ADDR:	equ	106h
CSR_1SW1_IntCtrl_1_ADDR:	equ	107h
CSR_1SW1_IntEn_ADDR:	equ	5h
CSR_1SW1_MASK:	equ	10h
CSR_1SW1_MUXBusCtrl_ADDR:	equ	1d9h
; CSR_1SW1_Data access macros
;   GetCSR_1SW1_Data macro, return in a
macro GetCSR_1SW1_Data
	mov		a,[Port_1_Data_SHADE]
	and		a, 10h
endm
;   SetCSR_1SW1_Data macro
macro SetCSR_1SW1_Data
	or		[Port_1_Data_SHADE], 10h
	mov		reg[Port_1_Data], [Port_1_Data_SHADE]
endm
;   SetCSR_1SW1_Data macro
macro ClearCSR_1SW1_Data
	and		[Port_1_Data_SHADE], ~10h
	mov		reg[Port_1_Data], [Port_1_Data_SHADE]
endm

; CSR_1SW2 address and mask equates
CSR_1SW2_Data_ADDR:	equ	4h
CSR_1SW2_DriveMode_0_ADDR:	equ	104h
CSR_1SW2_DriveMode_1_ADDR:	equ	105h
CSR_1SW2_DriveMode_2_ADDR:	equ	7h
CSR_1SW2_GlobalSelect_ADDR:	equ	6h
CSR_1SW2_IntCtrl_0_ADDR:	equ	106h
CSR_1SW2_IntCtrl_1_ADDR:	equ	107h
CSR_1SW2_IntEn_ADDR:	equ	5h
CSR_1SW2_MASK:	equ	40h
CSR_1SW2_MUXBusCtrl_ADDR:	equ	1d9h
; CSR_1SW2_Data access macros
;   GetCSR_1SW2_Data macro, return in a
macro GetCSR_1SW2_Data
	mov		a,[Port_1_Data_SHADE]
	and		a, 40h
endm
;   SetCSR_1SW2_Data macro
macro SetCSR_1SW2_Data
	or		[Port_1_Data_SHADE], 40h
	mov		reg[Port_1_Data], [Port_1_Data_SHADE]
endm
;   SetCSR_1SW2_Data macro
macro ClearCSR_1SW2_Data
	and		[Port_1_Data_SHADE], ~40h
	mov		reg[Port_1_Data], [Port_1_Data_SHADE]
endm

; LCD_1D4 address and mask equates
LCD_1D4_Data_ADDR:	equ	8h
LCD_1D4_DriveMode_0_ADDR:	equ	108h
LCD_1D4_DriveMode_1_ADDR:	equ	109h
LCD_1D4_DriveMode_2_ADDR:	equ	bh
LCD_1D4_GlobalSelect_ADDR:	equ	ah
LCD_1D4_IntCtrl_0_ADDR:	equ	10ah
LCD_1D4_IntCtrl_1_ADDR:	equ	10bh
LCD_1D4_IntEn_ADDR:	equ	9h
LCD_1D4_MASK:	equ	1h
LCD_1D4_MUXBusCtrl_ADDR:	equ	1dah
; LCD_1D4_Data access macros
;   GetLCD_1D4_Data macro, return in a
macro GetLCD_1D4_Data
	mov		a,[Port_2_Data_SHADE]
	and		a, 1h
endm
;   SetLCD_1D4_Data macro
macro SetLCD_1D4_Data
	or		[Port_2_Data_SHADE], 1h
	mov		reg[Port_2_Data], [Port_2_Data_SHADE]
endm
;   SetLCD_1D4_Data macro
macro ClearLCD_1D4_Data
	and		[Port_2_Data_SHADE], ~1h
	mov		reg[Port_2_Data], [Port_2_Data_SHADE]
endm

; LCD_1D4_DriveMode_0 access macros
;   GetLCD_1D4_DriveMode_0 macro, return in a
macro GetLCD_1D4_DriveMode_0
	mov		a,[Port_2_DriveMode_0_SHADE]
	and		a, 1h
endm
;   SetLCD_1D4_DriveMode_0 macro
macro SetLCD_1D4_DriveMode_0
	or		[Port_2_DriveMode_0_SHADE], 1h
	mov		reg[Port_2_DriveMode_0], [Port_2_DriveMode_0_SHADE]
endm
;   SetLCD_1D4_DriveMode_0 macro
macro ClearLCD_1D4_DriveMode_0
	and		[Port_2_DriveMode_0_SHADE], ~1h
	mov		reg[Port_2_DriveMode_0], [Port_2_DriveMode_0_SHADE]
endm

; LCD_1D4_DriveMode_1 access macros
;   GetLCD_1D4_DriveMode_1 macro, return in a
macro GetLCD_1D4_DriveMode_1
	mov		a,[Port_2_DriveMode_1_SHADE]
	and		a, 1h
endm
;   SetLCD_1D4_DriveMode_1 macro
macro SetLCD_1D4_DriveMode_1
	or		[Port_2_DriveMode_1_SHADE], 1h
	mov		reg[Port_2_DriveMode_1], [Port_2_DriveMode_1_SHADE]
endm
;   SetLCD_1D4_DriveMode_1 macro
macro ClearLCD_1D4_DriveMode_1
	and		[Port_2_DriveMode_1_SHADE], ~1h
	mov		reg[Port_2_DriveMode_1], [Port_2_DriveMode_1_SHADE]
endm

; LCD_1D5 address and mask equates
LCD_1D5_Data_ADDR:	equ	8h