;;*****************************************************************************
;;*****************************************************************************
;;  FILENAME:   CSR_1.inc
;;   Version: 1.1, Updated on 2005/10/13 at 09:13:22
;;  Generated by PSoC Designer ver 4.2  b1013 : 02 September, 2004
;;
;;  DESCRIPTION:
;;    Assembler declarations for the CSR user module interface
;;    for the 21xxx PSoC family of devices.
;;-----------------------------------------------------------------------------
;;  Copyright (c) Cypress MicroSystems 2000-2005. All Rights Reserved.
;;*****************************************************************************
;;*****************************************************************************


CSR_1_CTR_START_BIT:                   equ 0x01   ; CTR Control register start bit
CSR_1_PWM_START_BIT:                   equ 0x01   ; PWM Control register start bit
CSR_1_CMP_START_BIT:                   equ 0x01   ; CMP CR2 register start bit
CSR_1_SCAN_INT_REG:                    equ 0x0e1
CSR_1_SCAN_INT_MASK:                   equ 0x01

CSR_1_Method:                          equ 0
CSR_1_Method_Freq:                     equ 0
CSR_1_Method_Period:                   equ 1

;--------------------------------------------------
; Constants for CSR_1 API's
;--------------------------------------------------
CSR_1_SCAN_CONTINUOUS:                 equ 0x01
CSR_1_SCAN_ONCE:                       equ 0x00

CSR_1_SCAN_ACTIVE:                     equ 0x10   ; Set when scanning is active
CSR_1_SCAN_SET_COMPLETE:               equ 0x20   ; Set each time a set of keys is scanned.

CSR_1_ButtonCount:                     equ 0x3
CSR_1_SliderCount:                     equ 0x1
CSR_1_TotalSwitchCount:                equ 0xb

CSR_1_DAC_LOW:                         equ 0x00
CSR_1_DAC_HIGH:                        equ 0x01

CSR_1_ESD_DETECTION:                   equ 0x0
CSR_1_BUTTONS_EXIST:                   equ 0x3
CSR_1_SLIDERS_EXIST:                   equ 0x1

;--------------------------------------------------
; Registers Address Constants for CSR_1
;--------------------------------------------------

CSR_1_PWM_FUNC_REG:                    equ 0x20             ; PWM Function Reg
CSR_1_PWM_IN_REG:                      equ 0x21             ; PWM Input Reg 
CSR_1_PWM_OUT_REG:                     equ 0x22             ; PWM Output Reg       
CSR_1_PWM_COUNTER_REG:                 equ 0x20             ; PWM Counter Reg       
CSR_1_PWM_PERIOD_REG:                  equ 0x21             ; PWM Period Reg       
CSR_1_PWM_COMPARE_REG:                 equ 0x22             ; PWM Compare Reg       
CSR_1_PWM_CONTROL_REG:                 equ 0x23             ; PWM Control Reg       

CSR_1_ACE_CONTROL1_REG:                equ 0x72             ; PWM Function Register
CSR_1_ACE_CONTROL2_REG:                equ 0x73             ; PWM Function Register

CSR_1_CTR_COUNTER_LSB_REG:             equ 0x24             ; CTR LSB Counter Reg  
CSR_1_CTR_PERIOD_LSB_REG:              equ 0x25             ; CTR LSB Period Reg
CSR_1_CTR_COMPARE_LSB_REG:             equ 0x26             ; CTR LSB Compare Reg
CSR_1_CTR_CONTROL_LSB_REG:             equ 0x27             ; CTR LSB Control Reg
CSR_1_CTR_FUNC_LSB_REG:                equ 0x24             ; CTR LSB Function Reg
CSR_1_CTR_INPUT_LSB_REG:               equ 0x25             ; CTR LSB Input Reg
CSR_1_CTR_OUTPUT_LSB_REG:              equ 0x26             ; CTR LSB Output Reg

CSR_1_CTR_COUNTER_MSB_REG:             equ 0x28             ; CTR MSB Counter Reg  
CSR_1_CTR_PERIOD_MSB_REG:              equ 0x29             ; CTR MSB Period Reg
CSR_1_CTR_COMPARE_MSB_REG:             equ 0x2a             ; CTR MSB Compare Reg
CSR_1_CTR_CONTROL_MSB_REG:             equ 0x2b             ; CTR MSB Control Reg
CSR_1_CTR_FUNC_MSB_REG:                equ 0x28             ; CTR MSB Function Reg
CSR_1_CTR_INPUT_MSB_REG:               equ 0x29             ; CTR MSB Input Reg
CSR_1_CTR_OUTPUT_MSB_REG:              equ 0x2a             ; CTR MSB Output Reg


DR_OFFSET:                             equ 0x00
DM0_OFFSET:                            equ 0x00             ; Bank 1
DM1_OFFSET:                            equ 0x01             ; Bank 1
DM2_OFFSET:                            equ 0x03             ; Bank 0
MUX_OFFSET:                            equ MUX_CR0          ; Bank 1

;--------------------------------------------------
; CSR_1 Macro 'Functions'
;--------------------------------------------------

   macro CSR_1_Start_M
   or    reg[CSR_1_CTR_CONTROL_LSB_REG],  CSR_1_CTR_START_BIT
   or    reg[CSR_1_PWM_CONTROL_REG],      CSR_1_PWM_START_BIT
   endm

   macro CSR_1_Start_Counter_M
   or    reg[CSR_1_CTR_CONTROL_LSB_REG],  CSR_1_CTR_START_BIT
   endm

   macro CSR_1_Start_CMP_M
   mov   reg[CSR_1_ACE_CONTROL2_REG],     CSR_1_CMP_START_BIT
   endm

   macro CSR_1_Stop_M
   and   reg[CSR_1_PWM_CONTROL_REG],     ~CSR_1_PWM_START_BIT
   and   reg[CSR_1_CTR_CONTROL_LSB_REG], ~CSR_1_CTR_START_BIT
   endm

   macro CSR_1_Stop_Counter_M
   and   reg[CSR_1_CTR_CONTROL_LSB_REG], ~CSR_1_CTR_START_BIT
   endm

   macro CSR_1_Stop_CMP_M
   mov   reg[CSR_1_ACE_CONTROL2_REG],    ~CSR_1_CMP_START_BIT
   endm

   macro CSR_1_EnableInt_M
   M8C_EnableIntMask CSR_1_SCAN_INT_REG, CSR_1_SCAN_INT_MASK
   endm

   macro CSR_1_DisableInt_M
   M8C_DisableIntMask CSR_1_SCAN_INT_REG, CSR_1_SCAN_INT_MASK
   endm      

; end of file CSR_1.inc