?? csr_1.asm
字號(hào):
;;*****************************************************************************
;;*****************************************************************************
;; FILENAME: CSR_1.asm
;; Version: 1.1, Updated on 2005/10/13 at 09:13:22
;; Generated by PSoC Designer ver 4.2 b1013 : 02 September, 2004
;;
;; DESCRIPTION: CSR_1 User Module software implementation file
;; for the 21xxx PSoC family of devices.
;;-----------------------------------------------------------------------------
;; Copyright (c) Cypress MicroSystems 2000-2005. All Rights Reserved.
;;*****************************************************************************
;;*****************************************************************************
include "m8c.inc"
include "memory.inc"
include "CSR_1.inc"
;-----------------------------------------------
; Global Symbols
;-----------------------------------------------
export _CSR_1_Start
export CSR_1_Start
export _CSR_1_Stop
export CSR_1_Stop
export _CSR_1_StartScan
export CSR_1_StartScan
export _CSR_1_StopScan
export CSR_1_StopScan
export _CSR_1_GetScanStatus
export CSR_1_GetScanStatus
export _CSR_1_ClearSwitches
export CSR_1_ClearSwitches
export _CSR_1_iReadSwitch
export CSR_1_iReadSwitch
export _CSR_1_iGetPortPin
export CSR_1_iGetPortPin
export _CSR_1_EnableSwitch
export CSR_1_EnableSwitch
export _CSR_1_DisableSwitch
export CSR_1_DisableSwitch
export _CSR_1_SetDacCurrent
export CSR_1_SetDacCurrent
export _CSR_1_SetScanSpeed
export CSR_1_SetScanSpeed
export CSR_1_Switch_Table
export _CSR_1_Switch_Table
;-----------------------------------------------
; Variable Allocation
;-----------------------------------------------
AREA InterruptRAM (RAM, REL, CON)
CSR_1_bBitMask: BLK 1 ; Temp bitmask byte
_CSR_1_bSwitchNum: ; Current switch to scan
CSR_1_bSwitchNum: BLK 1
_CSR_1_bfStatus: ; Status byte
CSR_1_bfStatus: BLK 1
_CSR_1_bScanStart: ; First switch to scan
CSR_1_bScanStart: BLK 1
_CSR_1_bScanEnd: ; Last switch to scan
CSR_1_bScanEnd: BLK 1
_CSR_1_iaSwResult: ; Array of ints, one entry for each switch
CSR_1_iaSwResult: BLK (2*CSR_1_TotalSwitchCount)
_CSR_1_bPWMPeriod: ; Last switch to scan
CSR_1_bPWMPeriod: BLK 1
export CSR_1_bfStatus
export _CSR_1_bfStatus
export CSR_1_bSwitchNum
export _CSR_1_bSwitchNum
export CSR_1_iaSwResult
export _CSR_1_iaSwResult
export CSR_1_bScanStart
export _CSR_1_bScanStart
export CSR_1_bScanEnd
export _CSR_1_bScanEnd
export CSR_1_bPWMPeriod
export _CSR_1_bPWMPeriod
;@PSoC_UserCode_INIT@ (Do not change this line.)
;---------------------------------------------------
; Insert your custom declarations below this banner
;---------------------------------------------------
;------------------------
; User Includes
;------------------------
;------------------------
; User Constant Definitions
;------------------------
;------------------------
; User Variable Allocation
;------------------------
;---------------------------------------------------
; Insert your custom declarations above this banner
;---------------------------------------------------
;@PSoC_UserCode_END@ (Do not change this line.)
;------------------------
; Constant Definitions
;------------------------
AREA UserModules (ROM, REL, CON)
LSB: equ 1
MSB: equ 0
;---------------------------------
; Tables below generated by Wizard
;---------------------------------
; The Switch Table consist of two bytes for each switch. The first byte is the
; port number and the second is the bit mask for the bit. (Not the bit number)
; For example an entry for port 2 bit 3 (P2[3]) would be "dw 0x0208"
;
; This table consist of 0xb switches.
CSR_1_Switch_Table:
_CSR_1_Switch_Table:
dw 0x0104 // Port 1 Bit 2
dw 0x0110 // Port 1 Bit 4
dw 0x0140 // Port 1 Bit 6
dw 0x0001 // Port 0 Bit 0
dw 0x0002 // Port 0 Bit 1
dw 0x0004 // Port 0 Bit 2
dw 0x0008 // Port 0 Bit 3
dw 0x0010 // Port 0 Bit 4
dw 0x0020 // Port 0 Bit 5
dw 0x0040 // Port 0 Bit 6
dw 0x0080 // Port 0 Bit 7
.SECTION
;-----------------------------------------------------------------------------
; FUNCTION NAME: CSR_1_Start(void)
;
; DESCRIPTION:
; Initializes registers and turns on the comparitor.
;
;-----------------------------------------------------------------------------
;
; ARGUMENTS:
; None
;
; RETURNS: None.
; SIDE EFFECTS:
; The A and X registers may be modified by this or future implementations
; of this function. The same is true for all RAM page pointer registers in
; the Large Memory Model. When necessary, it is the calling function's
; responsibility to perserve their values across calls to fastcall16
; functions.
;
CSR_1_Start:
_CSR_1_Start:
RAM_PROLOGUE RAM_USE_CLASS_4
RAM_SETPAGE_CUR >CSR_1_bPWMPeriod
IF (CSR_1_Method)
// Period Method
mov [CSR_1_bPWMPeriod], 0x10
mov reg[CSR_1_PWM_PERIOD_REG],0x10 ; Set period (default to 10 cycles)
mov reg[CSR_1_PWM_COMPARE_REG],0x0E ; Set compare
mov reg[DAC_D], 0x80 ; Set Dac at medium level
ELSE
// Frequency Method
mov [CSR_1_bPWMPeriod], 0xFF
mov reg[CSR_1_PWM_PERIOD_REG],0xFF ; Set period
mov reg[CSR_1_PWM_COMPARE_REG],0xFD ; Set compare
mov reg[DAC_D], 0x80 ; Set Dac at medium level
ENDIF
mov reg[CMP_CR1],0x00 ; CLDIS0 - synced comparator input enters mux
mov reg[DEC_CR0],0x00 ; IGEN0 - output of comparator is not ANDed with a PWM
or reg[RDI0RI],0x03 ; Connect Row 0 to GIO0[4]
M8C_SetBank1
mov reg[DAC_CR],0x03 ; Range high = 0x08, Reset on G00[4] = 0x02, Dac Enable = 0x01
mov reg[CMP_GO_EN],0x08 ; GOO[4] out = 0x08, SEL0 - now sends output of IGEN0
or reg[GDI_O_OU],0x10 ; THIS SHOULD WORK IN THE XML DEBUG
mov reg[MUX_CR0],0x00 ; Make sure all switches are off by default
mov reg[MUX_CR1],0x00
mov reg[MUX_CR2],0x00
mov reg[MUX_CR3],0x00
or reg[CLK_CR3],0x04 ; Use Sysclock direct for Column 0
mov reg[CSR_1_PWM_OUT_REG],0x3C ; Output PWM compare to row 0, TC to row 3
IF (CSR_1_Method)
// Period Method
mov reg[CSR_1_PWM_IN_REG],0x1C ; Data = 0x10 (High) and Clock = 0x0C (Row_Input_0)
mov reg[CSR_1_CTR_INPUT_LSB_REG],0xFC ; Data = 0xF0 (Row_input_3) and Clock = 0x0X (SysClk direct see output reg)
mov reg[CSR_1_CTR_INPUT_MSB_REG],0x3C ; Data = 0x30 (Chain from LSB) and Clock = 0x0C (SysClk direct see output reg)
mov reg[CSR_1_CTR_OUTPUT_LSB_REG],0xC0 ; Use SysClk direct
mov reg[CSR_1_CTR_OUTPUT_MSB_REG],0xC0 ; Use SysClk direct
ELSE
// Frequency Method
mov reg[OSC_CR4],0x00 ; Use Sysclock as input to VC3
mov reg[OSC_CR3],0xFF ; Set VC3 to 255
mov reg[CSR_1_PWM_IN_REG],0x11 ; Data = 0x10 (High) and Clock = 0x01 (VC3)
mov reg[CSR_1_CTR_INPUT_LSB_REG],0xFC ; Data = 0x80 (Row_input_3) and Clock = 0x0C (Row_Input_0)
mov reg[CSR_1_CTR_INPUT_MSB_REG],0x3C ; Data = 0x30 (Chain from LSB) and Clock = 0x0C (Row_Input_0)
mov reg[CSR_1_CTR_OUTPUT_LSB_REG],0x00 ; Sync to SysClk and no outputs
mov reg[CSR_1_CTR_OUTPUT_MSB_REG],0x00 ; Sync to SysClk and no outputs
ENDIF
and reg[RDI0IS], ~0x80 ; Make sure input 'A' to LUT3 is RO[3]
and reg[RDI0LT1],~0xF0
or reg[RDI0LT1],0x40 ; Combine PWM compare and ~PWM TC running to GPIO: ~A&B (LUT3)
and reg[RDI0RO1],~0xF0
or reg[RDI0RO1],0x80 ; Output LUT3 to global out odd 7
or reg[GDI_O_OU],0x80 ; Drive global out odd 7 onto global in odd 7
or reg[RDI0RI],0xC0 ; Row input 3 comes from global in odd 7
and reg[RDI0SYN],~0x08 ; Row input 3 passes with synchronization
M8C_SetBank0
call CSR_1_ClearSwitches ; Loop through all keys and deactivate
; This also puts pin in proper mode.
RAM_EPILOGUE RAM_USE_CLASS_4
ret
.ENDSECTION
.SECTION
;-----------------------------------------------------------------------------
; FUNCTION NAME: CSR_1_ClearSwitches(void)
;
; DESCRIPTION:
; Clears all switches to the non-sampling state.
;
;-----------------------------------------------------------------------------
;
; ARGUMENTS: None.
; RETURNS: None
; SIDE EFFECTS:
; The A and X registers may be modified by this or future implementations
; of this function. The same is true for all RAM page pointer registers in
; the Large Memory Model. When necessary, it is the calling function's
; responsibility to perserve their values across calls to fastcall16
; functions.
;
CSR_1_ClearSwitches:
_CSR_1_ClearSwitches:
RAM_PROLOGUE RAM_USE_CLASS_4
; Loop through all keys and deactivate
mov A,CSR_1_TotalSwitchCount ; Check if key value in range.
dec A
.InitLoop: ; Initialize all keys to be Disabled
push A
call CSR_1_iGetPortPin
call CSR_1_DisableSwitch
pop A
dec A
jnc .InitLoop
RAM_EPILOGUE RAM_USE_CLASS_4
ret
.ENDSECTION
.SECTION
;-----------------------------------------------------------------------------
; FUNCTION NAME: CSR_1_Stop(void)
;
; DESCRIPTION:
; Stop the switch scanner, disable interrupts and remove power to the analog
; block. This function also resets all switches to there inactive state.
;
;-----------------------------------------------------------------------------
;
; ARGUMENTS: None.
; RETURNS: Nothing.
; SIDE EFFECTS:
; The A and X registers may be modified by this or future implementations
; of this function. The same is true for all RAM page pointer registers in
; the Large Memory Model. When necessary, it is the calling function's
; responsibility to perserve their values across calls to fastcall16
; functions.
;
CSR_1_Stop:
_CSR_1_Stop:
RAM_PROLOGUE RAM_USE_CLASS_4
CSR_1_DisableInt_M ; Disable scanner interrupts
CSR_1_Stop_M ; Disable PWM scanner
mov reg[CSR_1_ACE_CONTROL2_REG],0x00 ; Turn off Power to analog block
call CSR_1_ClearSwitches ; Loop through all keys and deactivate
RAM_EPILOGUE RAM_USE_CLASS_4
ret
.ENDSECTION
.SECTION
;-----------------------------------------------------------------------------
; FUNCTION NAME: CSR_1_iGetPortPin(BYTE bSwitch)
;
; DESCRIPTION:
; Returns the port and pin mask from a given key number. This function
; uses the table CSR_1_Switch_Table to retreive this information.
;-----------------------------------------------------------------------------
;
; ARGUMENTS:
; A => Switch Number ( 0 to n )
; RETURNS:
; A <= Switch Bitmap
; X <= Port Number
;
; SIDE EFFECTS:
; The A and X registers may be modified by this or future implementations
; of this function. The same is true for all RAM page pointer registers in
; the Large Memory Model. When necessary, it is the calling function's
; responsibility to perserve their values across calls to fastcall16
; functions.
;
CSR_1_iGetPortPin:
_CSR_1_iGetPortPin:
RAM_PROLOGUE RAM_USE_CLASS_1
asl A ; multiply key by 2 since table is 2 bytes per key
mov X,A ; Copy index*2 in x for next value
index CSR_1_Switch_Table ; A contains the port value
swap A,X ; Place port value in X and index*2 in A
inc A ; Advance to next value (bitMask)
index CSR_1_Switch_Table ; A contains bitMask, X has port number
RAM_EPILOGUE RAM_USE_CLASS_1
ret
.ENDSECTION
.SECTION
;-----------------------------------------------------------------------------
; FUNCTION NAME: CSR_1_EnableSwitch(BYTE bSwitchMask, BYTE bPort)
;
; DESCRIPTION:
; Configures switch to be an input to be measure duirng next measurement
; cycle. This function does not clear the last switch.
; Place key port in Analog Hi-Z mode and enables the correct mux input.
;-----------------------------------------------------------------------------
;
; ARGUMENTS:
; X => Port Number for given key
; A => Bit mask for given switch
;
; RETURNS: none
;
; SIDE EFFECTS:
; The A and X registers may be modified by this or future implementations
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