#ifndef _SPR_H_#define _SPR_H_/********************************************************************************       COPYRIGHT (c) 2001 MOTOROLA INC.*       ALL RIGHTS RESERVED**       The code is the property of Sector Technology and is Motorola*       Confidential Proprietary Information.**       The copyright notice above does not evidence any*       actual or intended publication of such source code.** Filename:     $Source$* Author:       $Author$* Locker:       $Locker$* State:        $State$* Revision:     $Revision$** Functions:    ** History:      Use the RCS command rlog to display revision history*               information.** Description:  ** Notes:                *******************************************************************************/// PowerPC Special Purpose Registers#define SPR_XER		1#define SPR_LR		8#define SPR_CTR		9#define SPR_DAR		19#define SPR_DSISR	18#define SPR_DEC		22#define SPR_SDR1	25#define SPR_SRR0	26#define SPR_SRR1	27#define SPR_TBL		268#define SPR_TBU		269#define SPR_SPRG0	272#define SPR_SPRG1	273#define SPR_SPRG2	274#define SPR_SPRG3	275#define SPR_SVR		286#define SPR_PVR		287#define SPR_IBAT0U	528#define SPR_IBAT0L	529#define SPR_IBAT1U	530#define SPR_IBAT1L	531#define SPR_IBAT2U	532#define SPR_IBAT2L	533#define SPR_IBAT3U	534#define SPR_IBAT3L	535#define SPR_DBAT0U	536#define SPR_DBAT0L	537#define SPR_DBAT1U	538#define SPR_DBAT1L	539#define SPR_DBAT2U	540#define SPR_DBAT2L	541#define SPR_DBAT3U	542#define SPR_DBAT3L	543// PowerPC 603 Special Purpose Registers#define SPR_EAR		282#define SPR_DMISS	976#define SPR_DCMP	977#define SPR_HASH1	978#define SPR_HASH2	979#define SPR_IMISS	980#define SPR_ICMP	981#define SPR_RPA		982#define SPR_HID0	1008#define SPR_IABR	1010// PowerPC 603e Special Purpose Registers#define SPR_HID1	1009// PowerPC 603ei Special Purpose Registers#define SPR_CSRR0	58#define SPR_CSRR1	59#define SPR_SPRG4	276#define SPR_SPRG5	277#define SPR_SPRG6	278#define SPR_SPRG7	279#define SPR_IBCR	309#define SPR_DBCR	310#define SPR_MBAR	311#define SPR_DABR2	317#define SPR_IBAT4U	560#define SPR_IBAT4L	561#define SPR_IBAT5U	562#define SPR_IBAT5L	563#define SPR_IBAT6U	564#define SPR_IBAT6L	565#define SPR_IBAT7U	566#define SPR_IBAT7L	567#define SPR_DBAT4U	568#define SPR_DBAT4L	569#define SPR_DBAT5U	570#define SPR_DBAT5L	571#define SPR_DBAT6U	572#define SPR_DBAT6L	573#define SPR_DBAT7U	574#define SPR_DBAT7L	575#define SPR_HID2	1011#define SPR_DABR	1013#define SPR_IABR2	1018#define SPR_PIR		1023// XER bit definitions#define MPC_XER_SO		0x80000000UL#define MPC_XER_OV		0x40000000UL#define MPC_XER_CA		0x20000000UL#define MPC_XER_BCNT	0x000000FFUL// MSR bit definitions#define MSR_POW			0x00040000UL#define MSR_TGPR		0x00020000UL#define MSR_ILE			0x00010000UL#define MSR_EE			0x00008000UL#define MSR_PR			0x00004000UL#define MSR_FP			0x00002000UL#define MSR_ME			0x00001000UL#define MSR_FE0			0x00000800UL#define MSR_SE			0x00000400UL#define MSR_BE			0x00000200UL#define MSR_FE1			0x00000100UL#define MSR_CE			0x00000080UL#define MSR_IP			0x00000040UL#define MSR_IR			0x00000020UL#define MSR_DR			0x00000010UL#define MSR_RI			0x00000002UL#define MSR_LE			0x00000001UL// PVR bit definitions#define PVR_CID			0xF0000000UL#define PVR_PT			0x03C00000UL#define PVR_PID			0x003F0000UL#define PVR_PROC		0x0000F000UL#define PVR_MFG			0x00000F00UL#define PVR_MJREV		0x000000F0UL#define PVR_MNREV		0x0000000FUL// SVR bit definitions#define SVR_CID			0xF0000000UL#define SVR_PT			0x0FC00000UL#define SVR_SID			0x003F0000UL#define SVR_PROC		0x0000F000UL#define SVR_MFG			0x00000F00UL#define SVR_MJREV		0x000000F0UL#define SVR_MNREV		0x0000000FUL// HID0 bit definitions#define HID0_EMCP		0x80000000UL#define HID0_EBA		0x20000000UL#define HID0_EBD		0x10000000UL#define HID0_SBCLK		0x08000000UL#define HID0_ECLK		0x02000000UL#define HID0_PAR		0x01000000UL#define HID0_DOZE		0x00800000UL#define HID0_NAP		0x00400000UL#define HID0_SLEEP		0x00200000UL#define HID0_DPM		0x00100000UL#define HID0_RISEG		0x00080000UL#define HID0_NHR		0x00010000UL#define HID0_ICE		0x00008000UL#define HID0_DCE		0x00004000UL#define HID0_ILOCK		0x00002000UL#define HID0_DLOCK		0x00001000UL#define HID0_ICFI		0x00000800UL#define HID0_DCFI		0x00000400UL#define HID0_IFEM		0x00000080UL#define HID0_FBIOB		0x00000010UL#define HID0_ABE		0x00000008UL#define HID0_NOOPTI		0x00000001UL// HID1 bit definitions#define HID1_PC			0xF8000000UL#define HID1_PC0		0x80000000UL#define HID1_PC1		0x40000000UL#define HID1_PC2		0x20000000UL#define HID1_PC3		0x10000000UL#define HID1_PC4		0x08000000UL#define HID1_FPD		0x00000001UL// HID2 bit definitions#define HID2_LET		0x08000000UL#define HID2_HBE		0x00040000UL#define HID2_SFP		0x00010000UL#define HID2_IWLCK		0x0000E000UL#define HID2_DWLCK		0x000000E0UL// BAT bit definitions#define BATU_BEPI		0xFFFE0000UL#define BATU_BL_128K	0x00000000UL#define BATU_BL_256K	0x00000004UL#define BATU_BL_512K	0x0000000CUL#define BATU_BL_1M		0x0000001CUL#define BATU_BL_2M		0x0000003CUL#define BATU_BL_4M		0x0000007CUL#define BATU_BL_8M		0x000000FCUL#define BATU_BL_16M		0x000001FCUL#define BATU_BL_32M		0x000003FCUL#define BATU_BL_64M		0x000007FCUL#define BATU_BL_128M	0x00000FFCUL#define BATU_BL_256M	0x00001FFCUL#define BATU_SUPERVISOR	0x00000002UL#define BATU_USER		0x00000001UL#define BATU_INVALID	0x00000000UL#define BATL_BRPN		0xFFFE0000UL#define BATL_WRITE_THR	0x00000040UL#define BATL_CACHE_INH	0x00000020UL#define BATL_COHERENCY	0x00000010UL#define BATL_GUARDED	0x00000008UL#define BATL_READ_WRITE	0x00000002UL#define BATL_READ_ONLY	0x00000001UL#define BATL_NO_ACCESS	0x00000000UL#endif