#setMMRBaseAddr 0x0f000000
writereg	MBAR	0x0f000000

writemmr	IMMR	0x0F000000

# SYPCR: turn off watchdog timer
writemmr	SYPCR		0xffffffc3

writemmr	SCCR	0x00000001

writemmr	RMR			0x0001		# RMR=1: Set checkstop reset enable in the Reset Mode Register
writemmr	MPTPR		0x2800		# MPTPR: Set the Memory Periodic Timer Prescaler

# CS0 is flash at 0xff800000, 32-bit port, no error checking, writable, GPCM, 60x bus, valid
writemmr	BR0		0xff801801
writemmr	OR0		0xff800876


# CS1 is board control & status registers at 0x04500000 
writemmr	BR1		0x04501801
writemmr	OR1		0xffff8010


# CS2 is SDRAM, 64-bit port at 0x00000000
writemmr	OR2		0xfc002cc0
writemmr	BR2		0x00000041

writemmr	PSRT		0x13
writemmr	MPTPR		0x2800

# precharge all banks
writemmr	PSDMR		0x834f36a3
writemmr	PSDMR		0xab4f36a3 

# perform an access
writemem.b	0x00000000	0x00

# cbr refresh
writemmr	PSDMR		0x8b4f36a3

# perform 8 accesses
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF

; Issue Mode register write
writemmr	PSDMR		0x9b4f36a3
writemem.b	0x00000190	0x00
writemmr	PSDMR		0xc34f36a3

writemmr	TESCR1	0x00004000 
writemmr	TESCR2	0x00000000 

writemmr	LSRT		0

# PCI init
writemmr	OR3		0xFFFF8010
writemmr	BR3		0x04731801

#writemmr	LURT		0x00

writereg	MSR		0x00003002