#ifndef _I2C_MASTER_H_
#define _I2C_MASTER_H_

/*
 * Definitions for the Opencores i2c master core
 */

/* --- Definitions for i2c master's registers --- */
  
/* ----- Read-write access                                            */

#define OC_I2C_PRER_LO 0x00     /* Low byte clock prescaler register  */  
#define OC_I2C_PRER_HI 0x01     /* High byte clock prescaler register */  
#define OC_I2C_CTR     0x02     /* Control register                   */  
                    
/* ----- Write-only registers                                         */
                    
#define OC_I2C_TXR     0x03     /* Transmit byte register             */  
#define OC_I2C_CR      0x04     /* Command register                   */  
  
/* ----- Read-only registers                                          */
                    
#define OC_I2C_RXR     0x03     /* Receive byte register              */
#define OC_I2C_SR      0x04     /* Status register                    */
  
/* ----- Bits definition                                              */
  
/* ----- Control register                                             */
  
#define OC_I2C_EN (1<<7)        /* Core enable bit:                   */
                                /*      1 - core is enabled           */
                                /*      0 - core is disabled          */
#define OC_I2C_IEN (1<<6)       /* Interrupt enable bit               */
                                /*      1 - Interrupt enabled         */
                                /*      0 - Interrupt disabled        */
                                /* Other bits in CR are reserved      */

/* ----- Command register bits                                        */
 
#define OC_I2C_STA (1<<7)       /* Generate (repeated) start condition*/
#define OC_I2C_STO (1<<6)       /* Generate stop condition            */
#define OC_I2C_RD  (1<<5)       /* Read from slave                    */
#define OC_I2C_WR  (1<<4)       /* Write to slave                     */
#define OC_I2C_ACK (1<<3)       /* Acknowledge from slave             */
                                /*      1 - ACK                       */
                                /*      0 - NACK                      */
#define OC_I2C_IACK (1<<0)      /* Interrupt acknowledge              */

/* ----- Status register bits                                         */

#define OC_I2C_RXACK (1<<7)     /* ACK received from slave            */
                                /*      1 - ACK                       */
                                /*      0 - NACK                      */
#define OC_I2C_BUSY  (1<<6)     /* Busy bit                           */
#define OC_I2C_TIP   (1<<1)     /* Transfer in progress               */
#define OC_I2C_IF    (1<<0)     /* Interrupt flag                     */

/* bit testing and setting macros                                     */

#define OC_ISSET(reg,bitmask)       ((reg)&(bitmask))
#define OC_ISCLEAR(reg,bitmask)     (!(OC_ISSET(reg,bitmask)))
#define OC_BITSET(reg,bitmask)      ((reg)|(bitmask))
#define OC_BITCLEAR(reg,bitmask)    ((reg)|(~(bitmask)))
#define OC_BITTOGGLE(reg,bitmask)   ((reg)^(bitmask))
#define OC_REGMOVE(reg,value)       ((reg)=(value))

#endif //_I2C_MASTER_H_