?? iolpc2888_fields.h
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/*
*********************************************************************************************************
* MICIRUM BOARD SUPPORT PACKAGE
*
* (c) Copyright 2003-2006; Micrium, Inc.; Weston, FL
*
* All rights reserved. Protected by international copyright laws.
* Knowledge of the source code may not be used to write a similar
* product. This file may only be used in accordance with a license
* and should not be redistributed in any way.
*********************************************************************************************************
*/
/*
*********************************************************************************************************
*
* BOARD SUPPORT PACKAGE
* REGISTER VALUE DEFINES
*
* NXP LPC2888
*
* Filename : bsp.h
* Version : V1.00
* Programmer(s) : Brian Nagel
*********************************************************************************************************
*/
#ifndef __IOLPC2888_FIELDS_H__
#define __IOLPC2888_FIELDS_H__
/*
*********************************************************************************************************
* CGU REGISTER VALUE DEFINES
*********************************************************************************************************
*/
#define CGU_FSR_32KHZ_OSC 0x00000000
#define CGU_FSR_FAST_OSC 0x00000001
#define CGU_FSR_MCICLK_PIN 0x00000002
#define CGU_FSR_DAIBCLK_PIN 0x00000003
#define CGU_FSR_DAIWS_PIN 0x00000004
#define CGU_FSR_HIGHSPEED_PLL 0x00000007
#define CGU_FSR_MAIN_PLL 0x00000008
#define CGU_SCR_ENF1 0x00000001
#define CGU_SCR_ENF2 0x00000002
#define CGU_SCR_SCRES 0x00000004
#define CGU_SCR_SCSTOP 0x00000008
#define CGU_SSR_ENF1 0x00000001
#define CGU_SSR_ENF2 0x00000002
#define CGU_BCR_FDRUN 0x00000001
#define CGU_FDCR_FDRUN 0x00000001
#define CGU_FDCR_FDRES 0x00000002
#define CGU_FDCR_FDSTRCH 0x00000004
#define CGU_FDCR_MADD 0x000007F8
#define CGU_FDCR_MSUB 0x0007F800
#define CGU_PCR_PCRUN 0x00000001
#define CGU_PCR_PCAUTO 0x00000002
#define CGU_PCR_WAKE_EN 0x00000004
#define CGU_PCR_EXTEN_EN 0x00000008
#define CGU_PCR_ENOUT_EN 0x00000010
#define CGU_PSR_PSACTIVE 0x00000001
#define CGU_PSR_PSAWAKE 0x00000002
#define CGU_ESR_SSCLOCK 0x00000000
#define CGU_ESR_FD0 0x00000001
#define CGU_ESR_FD1 0x00000003
#define CGU_ESR_FD2 0x00000005
#define CGU_ESR_FD3 0x00000007
#define CGU_ESR_FD4 0x00000009
#define CGU_ESR_FD5 0x0000000B
/*
*********************************************************************************************************
* ADC REGISTER VALUE DEFINES
*********************************************************************************************************
*/
#define ADCCON_SELVREF 0x00000001
#define ADCCON_ADCENAB 0x00000002
#define ADCCON_CSCAN 0x00000004
#define ADCCON_ADCSTRT 0x00000008
#define ADCCON_ADCBUSY 0x00000010
#define ADCSEL_SEL0 0x0000000F
#define ADCSEL_SEL1 0x000000F0
#define ADCSEL_SEL2 0x00000F00
#define ADCSEL_SEL3 0x0000F000
#define ADCSEL_SEL4 0x000F0000
#define ADCSEL_SEL5 0x00F00000
/*
********************************************************************************************************
* MCI REGISTER VALUE DEFINES
********************************************************************************************************
*/
#define MCIPOWER_POWEROFF 0x00000000
#define MCIPOWER_POWERUP 0x00000002
#define MCIPOWER_POWERON 0x00000003
#define MCIPOWER_OPENDRAIN 0x00000020
#define MCICLOCK_CLKDIV(x) ((x) & 0x000000FF)
#define MCICLOCK_CLKENAB 0x00000100
#define MCICLOCK_PWRSAVE 0x00000200
#define MCICLOCK_BYPASS 0x00000400
#define MCICLOCK_WIDEBUS 0x00000800
#define MCICOMMAND_CMDINDEX(x) ((x) & 0x0000003F)
#define MCICOMMAND_RESPONSE 0x00000040
#define MCICOMMAND_LONGRSP 0x00000080
#define MCICOMMAND_INTERRUPT 0x00000100
#define MCICOMMAND_W8PEND 0x00000200
#define MCICOMMAND_CPSM_EN 0x00000400
#define MCIRESPCMD_RESPCMD(x) ((x) & 0x0000003F)
#define MCIRESPCMD_NONE 0x0000003F
#define MCIDATALENGTH_DATALENGTH(x) ((x) & 0x0000FFFF)
#define MCIDATACTRL_XFERENAB 0x00000001
#define MCIDATACTRL_DIRFROMCARD 0x00000002
#define MCIDATACTRL_DIRTOCARD 0x00000000
#define MCIDATACTRL_STREAMMODE 0x00000004
#define MCIDATACTRL_BLOCKMODE 0x00000000
#define MCIDATACTRL_DMAENABLE 0x00000008
#define MCIDATACTRL_BLOCKSIZE(x) (((x) & 0x0000000F) << 4)
/* An error exists in the LPC2888 documentation with . . . */
/* . . .respect to this register. The bit assignments . . .*/
/* . . .for RXFIFOEMPTY and RXDATAAVLBL are switched. . . . */
/* . . .RXFIFOEMPTY should be bit 19; RXDATAAVLBL . . . */
/* . . .be bit 21. */
#define MCISTATUS_CMDCRCFAIL 0x00000001
#define MCISTATUS_DATACRCFAIL 0x00000002
#define MCISTATUS_CMDTIMEOUT 0x00000004
#define MCISTATUS_DATATIMEOUT 0x00000008
#define MCISTATUS_TXUNDERRUN 0x00000010
#define MCISTATUS_RXOVERRUN 0x00000020
#define MCISTATUS_CMDRESPEND 0x00000040
#define MCISTATUS_CMDSENT 0x00000080
#define MCISTATUS_DATAEND 0x00000100
#define MCISTATUS_STARTBITERR 0x00000200
#define MCISTATUS_DATABLOCKEND 0x00000400
#define MCISTATUS_CMDACTIVE 0x00000800
#define MCISTATUS_TXACTIVE 0x00001000
#define MCISTATUS_RXACTIVE 0x00002000
#define MCISTATUS_TXFIFOHALFEMPTY 0x00004000
#define MCISTATUS_RXFIFOHALFFULL 0x00008000
#define MCISTATUS_TXFIFOFULL 0x00010000
#define MCISTATUS_RXFIFOFULL 0x00020000
#define MCISTATUS_TXFIFOEMPTY 0x00040000
#define MCISTATUS_RXFIFOEMPTY 0x00080000
#define MCISTATUS_TXDATAAVLBL 0x00100000
#define MCISTATUS_RXDATAAVLBL 0x00200000
#define MCICLEAR_CMDCRCFAILCLR 0x00000001
#define MCICLEAR_DATACRCFAILCLR 0x00000002
#define MCICLEAR_CMDTIMEOUTCLR 0x00000004
#define MCICLEAR_DATATIMEOUTCLR 0x00000008
#define MCICLEAR_TXUNDERRUNCLR 0x00000010
#define MCICLEAR_RXOVERRUNCLR 0x00000020
#define MCICLEAR_CMDRESPENDCLR 0x00000040
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