; SEG7DISP.bdf                     ; yes             ; User Block Diagram/Schematic File  ; E:/EDA/cdrom/mcu_usb_cpld/PLD實(shí)驗(yàn)/SEG7DISP/SEG7DISP.bdf ;
; Seg7_Dsp.vhd                     ; yes             ; Other                              ; E:/EDA/cdrom/mcu_usb_cpld/PLD實(shí)驗(yàn)/SEG7DISP/Seg7_Dsp.vhd ;
; fenping.vhd                      ; yes             ; Other                              ; E:/EDA/cdrom/mcu_usb_cpld/PLD實(shí)驗(yàn)/SEG7DISP/fenping.vhd  ;
; b3x8.vhd                         ; yes             ; Other                              ; E:/EDA/cdrom/mcu_usb_cpld/PLD實(shí)驗(yàn)/SEG7DISP/b3x8.vhd     ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------+


+----------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary              ;
+-----------------------------------+----------------------+
; Resource                          ; Usage                ;
+-----------------------------------+----------------------+
; Total logic elements              ; 43                   ;
; Total combinational functions     ; 43                   ;
;     -- Total 4-input functions    ; 7                    ;
;     -- Total 3-input functions    ; 8                    ;
;     -- Total 2-input functions    ; 0                    ;
;     -- Total 1-input functions    ; 27                   ;
;     -- Total 0-input functions    ; 1                    ;
; Combinational cells for routing   ; 0                    ;
; Total registers                   ; 27                   ;
; Total logic cells in carry chains ; 27                   ;
; I/O pins                          ; 21                   ;
; Maximum fan-out node              ; fenping:inst1|QN[15] ;
; Maximum fan-out                   ; 16                   ;
; Total fan-out                     ; 166                  ;
; Average fan-out                   ; 2.59                 ;
+-----------------------------------+----------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                          ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name     ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------+
; |SEG7DISP                  ; 43 (1)      ; 27           ; 0          ; 21   ; 0            ; 16 (1)       ; 0 (0)             ; 27 (0)           ; 27 (0)          ; |SEG7DISP               ;
;    |Seg7_Dsp:inst|         ; 18 (18)     ; 11           ; 0          ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 11 (11)          ; 11 (11)         ; |SEG7DISP|Seg7_Dsp:inst ;
;    |b3x8:inst4|            ; 8 (8)       ; 0            ; 0          ; 0    ; 0            ; 8 (8)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |SEG7DISP|b3x8:inst4    ;
;    |fenping:inst1|         ; 16 (16)     ; 16           ; 0          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 16 (16)          ; 16 (16)         ; |SEG7DISP|fenping:inst1 ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 27    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 16    ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                  ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output        ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------+
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |SEG7DISP|Seg7_Dsp:inst|SELOUT[2] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/EDA/cdrom/mcu_usb_cpld/PLD實(shí)驗(yàn)/SEG7DISP/SEG7DISP.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
    Info: Processing started: Sat Oct 21 18:06:48 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off SEG7DISP -c SEG7DISP
Info: Found 1 design units, including 1 entities, in source file SEG7DISP.bdf
    Info: Found entity 1: SEG7DISP
Info: Elaborating entity "SEG7DISP" for the top level hierarchy
Warning: Block or symbol "b3x8" of instance "inst4" overlaps another block or symbol
Info: Using design file Seg7_Dsp.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: Seg7_Dsp-a
    Info: Found entity 1: Seg7_Dsp
Info: Elaborating entity "Seg7_Dsp" for hierarchy "Seg7_Dsp:inst"
Info: Using design file fenping.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: fenping-behv
    Info: Found entity 1: fenping
Info: Elaborating entity "fenping" for hierarchy "fenping:inst1"
Warning: VHDL Process Statement warning at fenping.vhd(20): signal "SET" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Using design file b3x8.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: b3x8-behv1
    Info: Found entity 1: b3x8
Info: Elaborating entity "b3x8" for hierarchy "b3x8:inst4"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "SG[7]" stuck at VCC
Info: Implemented 64 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 20 output pins
    Info: Implemented 43 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
    Info: Processing ended: Sat Oct 21 18:06:49 2006
    Info: Elapsed time: 00:00:01