//-------------------------------------------
//Debounce circuit for one key_pressing
//Filename : debounce.v
//-------------------------------------------
module debounce
	(
		clk,
		rst,
		keyin,
		K_out
	);


	input	clk;
	input	rst;
	input	keyin;

	output	K_out;

//	3-stage delay
	reg	DEL1;
	reg	DEL2;
	reg	DEL3;

	wire	DJ;
	wire	DK;

always @(posedge clk or posedge rst)
begin
	if (rst)
		begin
     		DEL1 <= 1'b0;
	 		DEL2 <= 1'b0;
	 		DEL3 <= 1'b0;
		end
	else
		begin
			if (keyin == 1'b1)
				DEL1 <= 1'b1;
			else
				DEL1 <=1'b0;
			if (DEL1 ==1'b1)
				DEL2 <=1'b1;
			else
				DEL2 <= 1'b0;
			if (DEL2 ==1'b1)
				DEL3 <=1'b1;
			else
				DEL3 <= 1'b0;

		end
end

assign DJ = DEL1 & DEL2 & DEL3;

assign DK = ~(DEL1|DEL2|DEL3);

jkt jkf (.clk(clk), .rst(rst), .j(DJ), .k(DK), .q(K_out));

endmodule