/* * Memory map */#include "sizes.h"/* Processor memory map */#define DRAM_BASE0	0x30000000#define DRAM_BASE1	0x38000000#define DRAM_BASE	DRAM_BASE0#define DRAM_SIZE	SZ_64M/* RAM */#define MBOOT_RAM_SIZE	SZ_1M#define MBOOT_RAM_BASE	(DRAM_BASE + DRAM_SIZE - MBOOT_RAM_SIZE)#define MMU_TABLE_SIZE	SZ_16K#define MMU_TABLE_BASE	(MBOOT_RAM_BASE - MMU_TABLE_SIZE)#define SVC_STACK_SIZE	SZ_32K#define SVC_STACK_BASE	(MMU_TABLE_BASE - SVC_STACK_SIZE)#define IRQ_STACK_SIZE	SZ_32K#define IRQ_STACK_BASE	(SVC_STACK_BASE - IRQ_STACK_SIZE)#define RAM_SIZE	(IRQ_STACK_BASE - DRAM-BASE)#define RAM_BASE	DRAM_BASE/* uart */#define UART_BAUD_RATE	115200#define PCLK		50000000/* CPU clock */#define MDIV_200	0x5c#define PDIV_200	0x04#define SDIV_200	0x00/* initial values for DRAM */#define vBWSCON		0x22111110#define vBANKCON0	0x00000700#define vBANKCON1	0x00000700#define vBANKCON2	0x00000700#define vBANKCON3	0x00000700#define vBANKCON4	0x00000700#define vBANKCON5	0x00000700#define vBANKCON6	0x00018005#define vBANKCON7	0x00018005#define vREFRESH	0x008c04f4#define vBANKSIZE	0xb2#define vMRSRB6		0x30#define vMRSRB7		0x30/* clock */#define vLOCKTIME	0x00ffffff#define vCLKDIVN	0x03#define vMPLLCON_200	((MDIV_200 << 12) | (PDIV_200 << 4) | (SDIV_200))#define R1_iA	(1 << 31)  /* cp15 register 1 */#define R1_nF	(1 << 30)  /* cp15 register 1 *//* initial values for uart */#define vULCON0	0x03#define vUCON0	0x245#define vUFCON0	0x00#define vUMCON0	0x00/* initial values for GPIOs */#define vGPFCON		0x000055aa#define vGPFUP		0x000000ff#define vGPGCON		0x00008000#define vGPGUP		0x00000008#define vGPHCON		0x0016faaa#define vGPHUP		0x000007ff#define vEXTINT0	0x00000002#define vEXTINT1	0x00002000