//????GF_5 ???Galois field,??????ibit?GF_Cell?D-FF???
//GF_Cell????Xout??Yout??Xout&Yout?? D_FF ??4?????

//****************************main  module***********************************************************************//
module GF_5(D00,D01,D02,D03,D04,A0,A1,A2,A3,A4,B0,B1,B2,B3,B4,C0,C1,C2,C3,C4,clk);
input clk,D00,D01,D02,D03,D04,A0,A1,A2,A3,A4,B0,B1,B2,B3,B4;
output C0,C1,C2,C3,C4;
wire D10,D11,D12,D13,D14,D20,D21,D22,D23,D24,D30,D31,D32,D33,D34,D40,D41,D42,D43,D44;
wire Y00,Y01,Y02,Y03,Y10,Y11,Y12,Y13,Y20,Y21,Y22,Y23,Y30,Y31,Y32,Y33;
wire X01,X02,X03,X04,X11,X12,X13,X14,X21,X22,X23,X24,X31,X32,X33,X34;
wire s1,s2,s3,s4,w1,w2,w3,w4;


DFF DF1(clk,B4,s1);
DFF DF2(clk,B4,w1);
DFF2 DF3(clk,B3,w2);
DFF2 DF4(clk,A4,s2);
DFF3 DF5(clk,B3,s3);
DFF3 DF6(clk,A4,w3);
DFF4 DF7(clk,B4,w4);
DFF4 DF8(clk,A3,s4);

GF_Cell_NX U00(B0,A0,D00,Y00,D10,clk);  //No.1 colum
GF_Cell U01(A1,B0,D01,X01,Y01,D11,clk);
GF_Cell U02(B1,A1,D02,X02,Y02,D12,clk);
GF_Cell U03(A2,B1,D03,X03,Y03,D13,clk);
GF_Cell_NY U04(B2,A2,D04,X04,D14,clk);

GF_Cell_NX U10(X01,s1,D10,Y10,D20,clk);  //No.2 colunm
GF_Cell U11(X02,Y00,D11,X11,Y11,D21,clk);
GF_Cell U12(X03,Y01,D12,X12,Y12,D22,clk);
GF_Cell U13(X04,Y02,D13,X13,Y13,D23,clk); 
GF_Cell_NY U14(w1,Y03,D14,X14,D24,clk);

GF_Cell_NX U20(X11,s2,D20,Y20,D30,clk);  //No.3 colunm
GF_Cell U21(X12,Y10,D21,X21,Y21,D31,clk);
GF_Cell U22(X13,Y11,D22,X22,Y22,D32,clk);
GF_Cell U23(X14,Y12,D23,X23,Y23,D33,clk);
GF_Cell_NY U24(w2,Y13,D24,X24,D34,clk);
 
GF_Cell_NX U30(X21,s3,D30,Y30,D40,clk);  //No.4 colunm
GF_Cell U31(X22,Y20,D31,X31,Y31,D41,clk);
GF_Cell U32(X23,Y21,D32,X32,Y32,D42,clk);
GF_Cell U33(X24,Y22,D33,X33,Y33,D43,clk);
GF_Cell_NY U34(w3,Y23,D34,X34,D44,clk);

GF_Cell_NXY U40(X31,s4,D40,C0,clk);  //No.5 colunm
GF_Cell_NXY U41(X32,Y30,D41,C1,clk);
GF_Cell_NXY U42(X33,Y31,D42,C2,clk); 
GF_Cell_NXY U43(X34,Y32,D43,C3,clk);
GF_Cell_NXY U44(w4,Y33,D44,C4,clk);

endmodule
//***************************************************************************************************************//


//************************************************GF_cell********************************************************//
module GF_Cell(Xin,Yin,Din,Xout,Yout,Dout,clk);
output Xout,Yout,Dout;
input  Xin,Yin,Din;
input clk;
wire s1;
wire D1out,D2out,D3out;

assign s1=(Xin&Yin)^Din;

DFF D1(clk,Xin,D1out);
DFF D2(clk,Yin,D2out);
DFF D3(clk,s1,D3out);

assign Dout=D3out;
assign Xout=D1out;
assign Yout=D2out;
endmodule
//*******************************************GF_cell   NO   Xout***************************************************************//
module GF_Cell_NX(Xin,Yin,Din,Yout,Dout,clk);
output Yout,Dout;
input  Xin,Yin,Din;
input clk;
wire s1;
wire D2out,D3out;

assign s1=(Xin&Yin)^Din;

DFF D2(clk,Yin,D2out);
DFF D3(clk,s1,D3out);

assign Dout=D3out;
assign Yout=D2out;
endmodule
//*************************************************GF_cell   NO   Yout********************************************************//
module GF_Cell_NY(Xin,Yin,Din,Xout,Dout,clk);
output Xout,Dout;
input  Xin,Yin,Din;
input clk;
wire s1;
wire D1out,D3out;

assign s1=(Xin&Yin)^Din;

DFF D1(clk,Xin,D1out);
DFF D3(clk,s1,D3out);

assign Dout=D3out;
assign Xout=D1out;
endmodule
//*************************************************GF_cell   NO  Xout Yout****************************************//
module GF_Cell_NXY(Xin,Yin,Din,Dout,clk);
output Dout;
input  Xin,Yin,Din;
input clk;
wire s1;
wire D3out;

assign s1=(Xin&Yin)^Din;

DFF D1(clk,Xin,D1out);
DFF D3(clk,s1,D3out);

assign Dout=D3out;
endmodule

//*******************************************DFF cell************************************************************//
module DFF(clk,D,Q);
input clk;
input D;
output Q;
reg Q;

always @(posedge clk)
Q=D;
endmodule
//*******************************************2delay DFF cell**********************************************************//
module DFF2(clk,A,B);
input clk;
input A;
output B;
wire s1;
wire Dout;

DFF D1(clk,A,s1);
DFF D2(clk,s1,Dout);
assign B=Dout;
endmodule

//*******************************************3delay DFF cell**********************************************************//
module DFF3(clk,A,B);
input clk;
input A;
output B;
wire s1,s2;
wire Dout;

DFF D1(clk,A,s1);
DFF D2(clk,s1,s2);
DFF D3(clk,s2,Dout);
assign B=Dout;
endmodule
//*******************************************4delay DFF cell**********************************************************//
module DFF4(clk,A,B);
input clk;
input A;
output B;
wire s1,s2,s3;
wire Dout;

DFF D1(clk,A,s1);
DFF D2(clk,s1,s2);
DFF D3(clk,s2,s3);
DFF D4(clk,s3,Dout);
assign B=Dout;
endmodule