/* sngks32cSio.h - header file for Samsung KS32C serial driver *//* Copyright 1984-2001 Wind River Systems, Inc. */#include "copyright_wrs.h"/*modification history--------------------01c,16jul02,m_h  C++ protection01b,26apr01,m_h  convert tabs to spaces for readability01a,12apr01,m_h  created from snds100 template.*/#ifndef __INCsngks32cSioh#define __INCsngks32cSioh#ifdef __cplusplusextern "C" {#endif#include "sioLib.h"#include "sngks32c.h"#include "sngks32cTimer.h"#define AT91C_PIO_PER  	0x00 /* PIO Enable Register */#define AT91C_PIO_OER  	0x10 /* PIO Output Enable Register */#define AT91C_PIO_SODR 	0x30 /* PIO Set Output Data Register */#define AT91C_PIO_CODR 	0x34 /* PIO Clear Output Data Register */#define AT91C_PIO14		((unsigned int)1<<14)#define MODE_RS232 		0#define MODE_RS485		0xF/* 2	PIOA pins :31&30	used by GBGU as  TX & RX 	*/#define AT91C_PIOA_PDR  	0xFFFFF404	 /*  (PIOA) PIO Disable Register	*/#define AT91C_PIOA_ASR   	0xFFFFF470 	 /*  (PIOA) Select A Register		*/#define AT91C_PA31_DTXD     ((unsigned int) 1 << 31) /*   DBGU Debug Transmit Data	*/#define AT91C_PA30_DRXD     ((unsigned int) 1 << 30) /*   DBGU Debug Receive Data	*/#define AT91C_PA17_TXD0     ((unsigned int) 1 << 17) /*  USART 0 Transmit Data */#define AT91C_PA18_RXD0     ((unsigned int) 1 << 18) /*  USART 0 Receive Data */#if 0	AT91C_BASE_PIOA->PIO_PDR = AT91C_PA31_DTXD | AT91C_PA30_DRXD;  /* PA 31 & 30 */	AT91C_BASE_PIOA->PIO_ASR = AT91C_PA31_DTXD | AT91C_PA30_DRXD;	/*PIOa --TXD0,RXD0*/	AT91C_BASE_PIOA->PIO_PDR = (unsigned int)0x01<<17 | (unsigned int)0x01<<18;/*disable*/	AT91C_BASE_PIOA->PIO_ASR = (unsigned int)0x01<<17 | (unsigned int)0x01<<18;	/*PIOB--TXD1,RXD1---20\21*/	AT91C_BASE_PIOB->PIO_PDR = (unsigned int)0x01<<20 | (unsigned int)0x01<<21;/*disable*/	AT91C_BASE_PIOB->PIO_ASR = (unsigned int)0x01<<20 | (unsigned int)0x01<<21;	#endif/* Register offsets from Base Address  for DBGU peripheral*/#define AT91C_DBGU_C2R  	 0x44    /* (DBGU) Chip ID2 Register */#define AT91C_DBGU_THR  	 0x1C    /* (DBGU) Transmitter Holding Register */#define AT91C_DBGU_CSR 	 0x14    /* (DBGU) Channel Status Register */#define AT91C_DBGU_IDR  	 0x0C    /* (DBGU) Interrupt Disable Register */#define AT91C_DBGU_MR   	 0x04    /* (DBGU) Mode Register */#define AT91C_DBGU_FNTR 	 0x48    /* (DBGU) Force NTRST Register */#define AT91C_DBGU_C1R  	 0x40    /* (DBGU) Chip ID1 Register */#define AT91C_DBGU_BRGR 	 0x20    /* (DBGU) Baud Rate Generator Register */#define AT91C_DBGU_RHR  	 0x18    /* (DBGU) Receiver Holding Register */#define AT91C_DBGU_IMR  	 0x10    /* (DBGU) Interrupt Mask Register */#define AT91C_DBGU_IER  	 0x08    /* (DBGU) Interrupt Enable Register */#define AT91C_DBGU_CR   	 0x00    /* (DBGU) Control Register *//*	Register offsets from Base Address  for US peripheral	*/#define AT91C_US_TTGR  		0x28       			 /*  (US) Transmitter Time-guard Register    */#define AT91C_US_BRGR  		AT91C_DBGU_BRGR        /*  (US) Baud Rate Generator Register    */#define AT91C_US_RHR   		AT91C_DBGU_RHR        /*  (US) Receiver Holding Register    */#define AT91C_US_IMR   		AT91C_DBGU_IMR        /*  (US) Interrupt Mask Register    */#define AT91C_US_NER   		0x44       			 /*  (US) Nb Errors Register    */#define AT91C_US_RTOR  		0x24        			/*  (US) Receiver Time-out Register    */#define AT91C_US_XXR   		0x48        			/*  (US) XON_XOFF Register    */#define AT91C_US_FIDI  		0x40       			 /*  (US) FI_DI_Ratio Register    */#define AT91C_US_CR    		AT91C_DBGU_CR        /*  (US) Control Register    */#define AT91C_US_IER   		AT91C_DBGU_IER        /*  (US) Interrupt Enable Register    */#define AT91C_US_IF    		0x4C       			 /*  (US) IRDA_FILTER Register    */#define AT91C_US_MR   		AT91C_DBGU_MR        /*  (US) Mode Register    */#define AT91C_US_IDR   		AT91C_DBGU_IDR        /*  (US) Interrupt Disable Register    */#define AT91C_US_CSR   		AT91C_DBGU_CSR        /*  (US) Channel Status Register    */#define AT91C_US_THR   		AT91C_DBGU_THR        /*  (US) Transmitter Holding Register    *//*  -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */#define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2) /*  (DBGU) Reset Receiver */#define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3) /*  (DBGU) Reset Transmitter */#define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4) /*  (DBGU) Receiver Enable */#define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5) /*  (DBGU) Receiver Disable */#define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6) /*  (DBGU) Transmitter Enable */#define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7) /*  (DBGU) Transmitter Disable *//*  -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */#define AT91C_US_RSTSTA       ((unsigned int) 0x1 <<  8) /*  (USART) Reset Status Bits	*/#define AT91C_US_STTBRK       ((unsigned int) 0x1 <<  9) /*  (USART) Start Break	*/#define AT91C_US_STPBRK       ((unsigned int) 0x1 << 10) /*  (USART) Stop Break	*/#define AT91C_US_STTTO        ((unsigned int) 0x1 << 11) /*  (USART) Start Time-out	*/#define AT91C_US_SENDA        ((unsigned int) 0x1 << 12) /*  (USART) Send Address	*/#define AT91C_US_RSTIT        ((unsigned int) 0x1 << 13) /*  (USART) Reset Iterations	*/#define AT91C_US_RSTNACK      ((unsigned int) 0x1 << 14) /*  (USART) Reset Non Acknowledge	*/#define AT91C_US_RETTO        ((unsigned int) 0x1 << 15) /*  (USART) Rearm Time-out	*/#define AT91C_US_DTREN        ((unsigned int) 0x1 << 16) /*  (USART) Data Terminal readyEnable	*/#define AT91C_US_DTRDIS       ((unsigned int) 0x1 << 17) /*  (USART) Data Terminal ready Disable	*/#define AT91C_US_RTSEN        ((unsigned int) 0x1 << 18) /*  (USART) Request to Send enable	*/#define AT91C_US_RTSDIS       ((unsigned int) 0x1 << 19) /*  (USART) Request to Send Disable	*//*  -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */#define AT91C_US_PAR          ((unsigned int) 0x7 <<  9) /*  (DBGU) Parity type  */#define 	AT91C_US_PAR_EVEN                 ((unsigned int) 0x0 <<  9) /*  (DBGU) Even Parity */#define 	AT91C_US_PAR_ODD                  ((unsigned int) 0x1 <<  9) /*  (DBGU) Odd Parity	*/#define 	AT91C_US_PAR_SPACE                ((unsigned int) 0x2 <<  9) /*  (DBGU) Parity forced to 0 (Space)	*/#define 	AT91C_US_PAR_MARK                 ((unsigned int) 0x3 <<  9) /*  (DBGU) Parity forced to 1 (Mark)	*/#define 	AT91C_US_PAR_NONE                 ((unsigned int) 0x4 <<  9) /*  (DBGU) No Parity	*/#define 	AT91C_US_PAR_MULTI_DROP           ((unsigned int) 0x6 <<  9) /*  (DBGU) Multi-drop mode	*/#define AT91C_US_CHMODE       ((unsigned int) 0x3 << 14) /*  (DBGU) Channel Mode	*/#define 	AT91C_US_CHMODE_NORMAL               ((unsigned int) 0x0 << 14) /*  (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.	*/#define 	AT91C_US_CHMODE_AUTO                 ((unsigned int) 0x1 << 14) /*  (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.	*/#define 	AT91C_US_CHMODE_LOCAL                ((unsigned int) 0x2 << 14) /*  (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.	*/#define 	AT91C_US_CHMODE_REMOTE               ((unsigned int) 0x3 << 14) /*  (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.	*//*  -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */#define AT91C_US_USMODE       ((unsigned int) 0xF <<  0) /*  (USART) Usart mode	*/#define 	AT91C_US_USMODE_NORMAL               ((unsigned int) 0x0) /*  (USART) Normal	*/#define 	AT91C_US_USMODE_RS485                ((unsigned int) 0x1) /*  (USART) RS485	*/#define 	AT91C_US_USMODE_HWHSH                ((unsigned int) 0x2) /*  (USART) Hardware Handshaking	*/#define 	AT91C_US_USMODE_MODEM                ((unsigned int) 0x3) /*  (USART) Modem	*/#define 	AT91C_US_USMODE_ISO7816_0            ((unsigned int) 0x4) /*  (USART) ISO7816 protocol: T = 0		*/#define 	AT91C_US_USMODE_ISO7816_1            ((unsigned int) 0x6) /*  (USART) ISO7816 protocol: T = 1		*/#define 	AT91C_US_USMODE_IRDA                 ((unsigned int) 0x8) /*  (USART) IrDA		*/#define 	AT91C_US_USMODE_SWHSH                ((unsigned int) 0xC) /*  (USART) Software Handshaking	*/#define AT91C_US_CLKS         ((unsigned int) 0x3 <<  4) /*  (USART) Clock Selection (Baud Rate generator Input Clock		*/#define 	AT91C_US_CLKS_CLOCK                ((unsigned int) 0x0 <<  4) /*  (USART) Clock*/#define 	AT91C_US_CLKS_FDIV1                ((unsigned int) 0x1 <<  4) /*  (USART) fdiv1	*/#define 	AT91C_US_CLKS_SLOW                 ((unsigned int) 0x2 <<  4) /*  (USART) slow_clock (ARM)	*/#define 	AT91C_US_CLKS_EXT                  ((unsigned int) 0x3 <<  4) /*  (USART) External (SCK)	*/#define AT91C_US_CHRL         ((unsigned int) 0x3 <<  6) /*  (USART) Clock Selection (Baud Rate generator Input Clock	*/#define 	AT91C_US_CHRL_5_BITS               ((unsigned int) 0x0 <<  6) /*  (USART) Character Length: 5 bits	*/#define 	AT91C_US_CHRL_6_BITS               ((unsigned int) 0x1 <<  6) /*  (USART) Character Length: 6 bits	*/#define 	AT91C_US_CHRL_7_BITS               ((unsigned int) 0x2 <<  6) /*  (USART) Character Length: 7 bits	*/#define 	AT91C_US_CHRL_8_BITS               ((unsigned int) 0x3 <<  6) /*  (USART) Character Length: 8 bits	*/#define AT91C_US_SYNC         ((unsigned int) 0x1 <<  8) /*  (USART) Synchronous Mode Select	*/#define AT91C_US_NBSTOP       ((unsigned int) 0x3 << 12) /*  (USART) Number of Stop bits	*/#define 	AT91C_US_NBSTOP_1_BIT                ((unsigned int) 0x0 << 12) /*  (USART) 1 stop bit	*/#define 	AT91C_US_NBSTOP_15_BIT               ((unsigned int) 0x1 << 12) /*  (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits	*/#define 	AT91C_US_NBSTOP_2_BIT                ((unsigned int) 0x2 << 12) /*  (USART) 2 stop bits	*/#define AT91C_US_MSBF         ((unsigned int) 0x1 << 16) /*  (USART) Bit Order	*/#define AT91C_US_MODE9        ((unsigned int) 0x1 << 17) /*  (USART) 9-bit Character length		*/#define AT91C_US_CKLO         ((unsigned int) 0x1 << 18) /*  (USART) Clock Output Select	*/#define AT91C_US_OVER         ((unsigned int) 0x1 << 19) /*  (USART) Over Sampling Mode	*/#define AT91C_US_INACK        ((unsigned int) 0x1 << 20) /*  (USART) Inhibit Non Acknowledge	*/#define AT91C_US_DSNACK       ((unsigned int) 0x1 << 21) /*  (USART) Disable Successive NACK	*/#define AT91C_US_MAX_ITER     ((unsigned int) 0x1 << 24) /*  (USART) Number of Repetitions	*/#define AT91C_US_FILTER       ((unsigned int) 0x1 << 28) /*  (USART) Receive Line Filter	*//*  -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */#define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0) /*  (DBGU) RXRDY Interrupt  */#define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1) /*  (DBGU) TXRDY Interrupt  */#define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3) /*  (DBGU) End of Receive Transfer Interrupt  */#define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4) /*  (DBGU) End of Transmit Interrupt  */#define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5) /*  (DBGU) Overrun Interrupt  */#define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6) /*  (DBGU) Framing Error Interrupt  */#define AT91C_US_PARE         ((unsigned int) 0x1 <<  7) /*  (DBGU) Parity Error Interrupt  */#define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9) /*  (DBGU) TXEMPTY Interrupt  */#define AT91C_US_TXBUFE       ((unsigned int) 0x1 << 11) /*  (DBGU) TXBUFE Interrupt  */#define AT91C_US_RXBUFF       ((unsigned int) 0x1 << 12) /*  (DBGU) RXBUFF Interrupt  */#define AT91C_US_COMM_TX      ((unsigned int) 0x1 << 30) /*  (DBGU) COMM_TX Interrupt  */#define AT91C_US_COMM_RX      ((unsigned int) 0x1 << 31) /*  (DBGU) COMM_RX Interrupt  *//*  -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */#define AT91C_US_RXBRK        ((unsigned int) 0x1 <<  2) /*  (USART) Break Received/End of Break	*/#define AT91C_US_TIMEOUT      ((unsigned int) 0x1 <<  8) /*  (USART) Receiver Time-out	*/#define AT91C_US_ITERATION    ((unsigned int) 0x1 << 10) /*  (USART) Max number of Repetitions Reached	*/#define AT91C_US_NACK         ((unsigned int) 0x1 << 13) /*  (USART) Non Acknowledge	*/#define AT91C_US_RIIC         ((unsigned int) 0x1 << 16) /*  (USART) Ring INdicator Input Change Flag	*/#define AT91C_US_DSRIC        ((unsigned int) 0x1 << 17) /*  (USART) Data Set Ready Input Change Flag	*/#define AT91C_US_DCDIC        ((unsigned int) 0x1 << 18) /*  (USART) Data Carrier Flag		*/#define AT91C_US_CTSIC        ((unsigned int) 0x1 << 19) /*  (USART) Clear To Send Input Change Flag	*//*  -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 	*//*  -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */