/*  -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 	*//*  -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 	*//*  -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 	*//*  -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */#define AT91C_US_RXREADY        ((unsigned int) 0x1 <<  0) /*  (DBGU) Receiver ready  	*/#define AT91C_US_TXREADY        ((unsigned int) 0x1 <<  1) /*  (DBGU) Transmitter ready *//*  -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 	*/#define AT91C_US_RI           ((unsigned int) 0x1 << 20) /*  (USART) Image of RI Input */#if 0#define AT91C_US_DSR          ((unsigned int) 0x1 << 21) /*  (USART) Image of DSR Input#define AT91C_US_DCD          ((unsigned int) 0x1 << 22) /*  (USART) Image of DCD Input#define AT91C_US_CTS          ((unsigned int) 0x1 << 23) /*  (USART) Image of CTS Input#define AT91C_US_FORCE_NTRST  ((unsigned int) 0x1 <<  0) /*  (DBGU) Force NTRST in JTAG		*//* DBGU Baud Rate Clock Divisor Constant Value :MCK = 18.432MHz,BAUD = MCK/(CD×16) */#define AT91C_CD_1200   960    /* Baud_Rate 1200*/#define AT91C_CD_2400   480    /* Baud_Rate 2400*/#define AT91C_CD_4800   240    /* Baud_Rate 4800*/#define AT91C_CD_9600   120    /* Baud_Rate 9600*/#define AT91C_CD_19200   60    /* Baud_Rate 19200*/#define AT91C_CD_38400   30    /* Baud_Rate 38400*/#define AT91C_CD_57600   20    /* Baud_Rate 57600*/#define AT91C_CD_115200  10    /* Baud_Rate 115200*/#define AT91C_CD_230400   5    /* Baud_Rate 230400*/#endif/* DBGU Baud Rate Clock Divisor Constant Value :MCK = 60MHz,BAUD = MCK/(CD×16) */#define MCLK 			92160000#define AT91C_CD_1200   	4800    /* Baud_Rate 1200*/#define AT91C_CD_2400    	2400    /* Baud_Rate 2400*/#define AT91C_CD_4800     1200    /* Baud_Rate 4800*/#define AT91C_CD_9600     600		/*MCLK/(16*9600)  */  /* Baud_Rate 9600*/#define AT91C_CD_19200   	300      /* Baud_Rate 19200*/#define AT91C_CD_38400    150     /* Baud_Rate 38400*/#define AT91C_CD_57600    100    /* Baud_Rate 57600*/#define AT91C_CD_115200   50	     /* Baud_Rate 115200*/#define AT91C_CD_230400   25    /* Baud_Rate 230400*//* Register offsets from Base Address*/#define SNGKS32C_ULCON         0x0000        /*UART Line Control Registers*/#define SNGKS32C_UCON          0x0004        /*UART Control Register */#define SNGKS32C_USTAT         0x0008        /*UART Status Register */#define SNGKS32C_UTXBUF        0x000c        /*UART Transmit Buffer Register*/#define SNGKS32C_URXBUF        0x0010        /*UART Receive Buffer Register*/#define SNGKS32C_UBRDIV        0x0014        /*UART Baud Rate Divisor Register*/#define SNGKS32C_BRDCNT        0x0018        /*UART Baud Rate Count Register */#define SNGKS32C_BRDCLK        0x001c        /*UART Baud Rate Clock Monitor*//* Bit definitions within ULCON0/1 Line Control Register*/#define PARITY_NONE     0x00            /* Set No Parity*/#define PARITY_ODD      0x20            /* Set Odd Parity*/#define PARITY_EVEN     0x28            /* Set Even Parity*/#define ONE_STOP        0x00            /* One Stop Bit*/#define WORD_LEN        0x03            /* Set Word Length 8*/#define INT_CLK         0x00            /* Internal Clock Mode */#define    EXT_CLK      0x40            /* External Clock Mode *//* Bit definitions within UCON0/1 Control Register*/#define UCON_RX          0x01            /* Receive Mode -Interrupt*/#define UCON_STAT_EN     0x04            /* Status Interrrupt -Enable*/#define UCON_TX          0x08            /* Transmit Mode-Interrupt*/#define UCON_TX_DIS      0x01            /* Transmit Interrupt -Disable*/#define UCON_DSR         0x20            /* Data Set Ready -Enable*/#define UCON_BREAK       0x40            /* Set Break*/#define UCON_RX_TX_RESET 0xe4            /* Rx and Tx Reset *//* Bit definitions within USTAT0/1 Status Register*/#define USTAT_DTR_LOW   0x10            /* DTR Enable */#define USTAT_DTR_HIGH  0x00            /* DTR Disable*/#define USTAT_TX_READY  0x40            /* Transmitter Ready for another char */#define USTAT_RX_AVAIL  0x20            /* Character has arrived*/ #define USTAT_OVER_ERR  0x01            /* Over Run Error*/#define USTAT_PAR_ERR   0x02            /* Parity Error*/#define USTAT_FRAME_ERR 0x04            /* Frame Error*/ #define USTAT_RX_READY  0x20            /* Receive Data Buffer*//* UART Baud Rate Divisor Time Constant Value (MCLK2 = 25MHz) */#define SNGKS32C_CNT0_1200   (1301<<4)    /* Baud_Rate 1200*/#define SNGKS32C_CNT0_2400    (650<<4)    /* Baud_Rate 2400*/#define SNGKS32C_CNT0_4800    (324<<4)    /* Baud_Rate 4800*/#define SNGKS32C_CNT0_9600    (162<<4)    /* Baud_Rate 9600*/#define SNGKS32C_CNT0_19200    (80<<4)    /* Baud_Rate 19200*/#define SNGKS32C_CNT0_38400    (40<<4)    /* Baud_Rate 38400*/#define SNGKS32C_CNT0_57600    (26<<4)    /* Baud_Rate 57600*/#define SNGKS32C_CNT0_115200   (13<<4)    /* Baud_Rate 115200*/#define SNGKS32C_CNT0_230400    (6<<4)    /* Baud_Rate 230400*/#define SNGKS32C_CNT0_460800    (2<<4)    /* Baud_Rate 460800*/#define SNGKS32C_CNT1_VAL         0x00    /* Baud Rate Divisor Value*//* device and channel structures */typedef struct    {    /* must be first */    SIO_CHAN        sio;        /* standard SIO_CHAN element */    /* callbacks */    STATUS            (*getTxChar) ();    STATUS            (*putRcvChar) ();    void *            getTxArg;    void *            putRcvArg;    /* register addresses */    UINT32 *          regs;        /*UART Registers*/    /*  interrupts */    UINT8             intLevel;     /* interrupt Level for this device*/    /* misc */    UINT32            regDelta;       /* register address spacing */    uint_t            options;        /* Hardware options */    int               mode;           /* current mode (interrupt or poll) */    int               baudRate;       /* input clock frequency */    char UARTmode;/*rs485/232*/    UINT32 pioBaseAdrs;    UINT32 pinValue;    } AT91C_CHAN;/* function prototypes */#if defined(__STDC__)extern void    at91cDevInit  (AT91C_CHAN *pChan); extern void    at91cDevInit2 (AT91C_CHAN *pChan); extern void    at91cInt   (AT91C_CHAN *pChan);#else   /* __STDC__ */extern void    at91cDevInit  ();extern void    at91cDevInit2 ();extern void    at91cInt  ();#endif  /* __STDC__ */#ifdef __cplusplus}#endif#endif  /* __INCsngks32cSioh */