#define	_ASMLANGUAGE#include "vxWorks.h"#include "sysLib.h"#include "asm.h"#include "regs.h"	#include "config.h"#include "AT91RM9200.h"        .data        .globl   VAR(copyright_wind_river)        .long    VAR(copyright_wind_river)/* internals */	.globl	FUNC(romInit)		/* start of system code */	.globl	VAR(sdata)		/* start of data */    .globl  _sdata/* externals */	.extern	FUNC(romStart)	/* system initialization routine */_sdata:VAR_LABEL(sdata)	.asciz	"start of data"	.balign	4/* variables */	.data	.long	0	.text	.balign 4_ARM_FUNCTION(romInit)_romInit:    B       coldcold:	MOV	r0, #BOOT_COLD	/* fall through to warm boot entry */warm:	B	start	.ascii   "Copyright uestc tantan,at91rm9200"	.balign 4start:/*all int disable*/	MRS	r1, cpsr	BIC	r1, r1, #MASK_MODE	ORR	r1, r1, #MODE_SVC32 | I_BIT | F_BIT	MSR	cpsr, r1		MOV    r13, r0    /* Save starttype in r13 so that r0 can be used for other purposes */    	LDR	   R0,=AT91C_AIC_ICCR		/*disable all int and clear all*/    	LDR	   R1,=0xffffffff    	STR	   R1,[r0]    	    	LDR	   R0,=AT91C_AIC_IDCR    	LDR	   R1,=0xffffffff    	STR	   R1,[r0]    	 		LDR	   R0,=AT91C_PIOC_ASR 		/*high 16bit data bus configuration*/		LDR	   R1,=0xFFFF0000		STR	   R1,[R0]			LDR	   R0,=AT91C_PIOC_BSR		LDR	   R1,=0x00000000		STR	   R1,[R0]			LDR	   R0,=AT91C_PIOC_PDR		LDR	   R1,=0xFFFF0000		STR	   R1,[R0]			LDR	   R0,=AT91C_EBI_CSA		/*sdram controller */		LDR	   R1,=0x00000002		STR	   R1,[R0]				LDR	   R0,=AT91C_EBI_CFGR		LDR	   R1,=0x00000000		STR	   R1,[R0]/*				MOV	   R0,#0xFF			WAIT:	SUB	   R0,R0,#1		BNE	   WAIT		*/				LDR	   R0,=AT91C_SDRC_CR				LDR	   R1,=0x2A88C155		STR	   R1,[R0]				LDR	   R0,=AT91C_SDRC_MR		LDR	   R1,=0x02			/*# All Banks Precharge*/		STR	   R1,[R0]/*				LDR	   R0,=0x20000000		LDR	   R1,=0		STR	   R1,[R0]*/				LDR	   R0,=AT91C_SDRC_MR		LDR	   R1,=0x04			/*# 8 次Refresh*/		STR	   R1,[R0]1:		LDR	   R0,=0x20000000				LDR	   R1,=0		STR	   R1,[R0]2:		LDR	   R0,=0x20000000		LDR	   R1,=0		STR	   R1,[R0]3:		LDR	   R0,=0x20000000				LDR	   R1,=0		STR	   R1,[R0]		LDR	   R0,=0x20000000		LDR	   R1,=0		STR	   R1,[R0]		5:		LDR	   R0,=0x20000000				LDR	   R1,=0		STR	   R1,[R0]				LDR	   R0,=0x20000000		LDR	   R1,=0		STR	   R1,[R0]		7:		LDR	   R0,=0x20000000				LDR	   R1,=0		STR	   R1,[R0]		8:		LDR	   R0,=0x20000000				LDR	   R1,=0		STR	   R1,[R0]				LDR	   R0,=AT91C_SDRC_MR		LDR	   R1,=0x03		STR	   R1,[R0]		LDR	   R0,=0x20000080		/*sdram mode reg set */		LDR	   R1,=0		STR	   R1,[R0]		LDR	   R0,=AT91C_SDRC_TR		LDR	   R1,=0x1F4		STR	   R1,[R0]/*				LDR	   R0,=0x20000000					LDR	   R1,=0		STR	   R1,[R0]*/			LDR	   R0,=AT91C_SDRC_MR		LDR	   R1,=0x0000		STR	   R1,[R0]/*		LDR	   R0,=0x20000000		LDR	   R1,=0		STR	   R1,[R0]*/				LDR	   R0,=AT91C_SMC2_CSR		LDR	   R1,=0x0000208f			/* #208f--16bit,2x8bit,		=308f--16bit,1x8bit    =408f--8bit */		STR	   R1,[R0]			LDR	   R0,=AT91C_CKGR_MOR		LDR	   R1,=0x0000FF01		STR	   R1,[R0]			LDR	   R0,=AT91C_CKGR_PLLAR		LDR	   R1,=0x20453E07			/* for X=18,432Mhz :PLLA= X*(MULA+1)/DIVA----184.32Mhz*/ 		STR	   R1,[R0]		LDR	   R0,=AT91C_CKGR_PLLBR		LDR	   R1,=0x10483E0e			/* for 18,432Mhz :PLLB/2--48Mhz FOR USB*/			STR	   R1,[R0]/*Note: Value to be written in PMC_MCKR must not be the same as current value in PMC_MCKR.	*/		LDR	   R0,=AT91C_PMC_MCKR		LDR	   R1,=0x00000000		STR	   R1,[R0]				LDR	   R0,=AT91C_PMC_MCKR		LDR	   R1,=0x00000102		/*MCK = PLLA/2 = 92.16Mhz*/		STR	   R1,[R0]		LDR	   R0,=AT91C_PMC_PCER		LDR	   R1,=0xFFFFFFFF		STR	   R1,[R0]    MOV    r0, r13        /* restore starttype to r0 from r13 */    LDR    sp, L$_STACK_ADDR    MOV    fp, #0            /* zero frame pointer */    /* jump to C entry point in ROM: routine - entry point + ROM base */#if	(ARM_THUMB)	LDR	r12, L$_rStrtInRom	ORR	r12, r12, #1		/* force Thumb state */	BX	r12#else	LDR	pc, L$_rStrtInRom#endif	/* (ARM_THUMB) */		L$_rStrtInRom:		.long	ROM_TEXT_ADRS + FUNC(romStart) - FUNC(romInit)L$_STACK_ADDR:		.long	STACK_ADRSL$_Hipos:		.long	FUNC(romStart)-FUNC(romInit)