?? sngks32cend.h
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/* sngks32cEnd.h - END style Ethernet interface header for Samsung ks32c *//* Copyright 1984-2002 Wind River Systems, Inc. */#include "copyright_wrs.h"/*modification history--------------------01d,14feb02,m_h error code field in END_DEVICE01c,27sep01,m_h big endian support01b,26apr01,m_h convert tabs to spaces for readability01a,12apr01,m_h created from snds100 template.*/#ifndef __INCsngks32cEndh#define __INCsngks32cEndh#ifdef __cplusplusextern "C" {#endif#include "end.h"#include "netBufLib.h"#include "sngks32c.h"/* EMAC PIO pins config ---about PIOA */#define AT91C_PIOA_PDR 0xFFFFF404 /* (PIOA) PIO Disable Register */#define AT91C_PIOA_ASR 0xFFFFF470 /* (PIOA) Select A Register */#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) /* Pin Controlled by PA7 */#define AT91C_PA7_ETXCK_EREFCK ((unsigned int) 1 << 7) /* Ethernet MAC Transmit Clock/Reference Clock */#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) /* Pin Controlled by PA8 */#define AT91C_PA8_ETXEN ((unsigned int) AT91C_PIO_PA8) /* Ethernet MAC Transmit Enable */#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) /* Pin Controlled by PA9 */#define AT91C_PA9_ETX0 ((unsigned int) AT91C_PIO_PA9) /* Ethernet MAC Transmit Data 0 */#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) /* Pin Controlled by PA10 */#define AT91C_PA10_ETX1 ((unsigned int) AT91C_PIO_PA10) /* Ethernet MAC Transmit Data 1 */#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) /* Pin Controlled by PA11 */#define AT91C_PA11_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PA11) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) /* Pin Controlled by PA12 */#define AT91C_PA12_ERX0 ((unsigned int) AT91C_PIO_PA12) /* Ethernet MAC Receive Data 0 */#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) /* Pin Controlled by PA13 */#define AT91C_PA13_ERX1 ((unsigned int) AT91C_PIO_PA13) /* Ethernet MAC Receive Data 1 */#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) /* Pin Controlled by PA14 */#define AT91C_PA14_ERXER ((unsigned int) AT91C_PIO_PA14) /* Ethernet MAC Receive Error */#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) /* Pin Controlled by PA15 */#define AT91C_PA15_EMDC ((unsigned int) AT91C_PIO_PA15) /* Ethernet MAC Management Data Clock */#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) /* Pin Controlled by PA16 */#define AT91C_PA16_EMDIO ((unsigned int) AT91C_PIO_PA16) /* Ethernet MAC Management Data Input/Output *//** PHY definitions **/#define PHY_CONTROL_REG 0#define PHY_ADDR 0#define _AUTO_NEGOTIATE 0x1000#define _10_MB_HDX 0#define _100_MB_FDX 0x2100#define _100_MB_HDX 0x2000#define _10_MB_FDX 0x100#define PHY_STS1_REG 1#define PHY_STS2_REG 17/* enable big/little endian register bits with this macro */#if (_BYTE_ORDER == _LITTLE_ENDIAN)#define ATMEND_ENDIAN 1#else#define ATMEND_ENDIAN 0#endif#if 0/** the following describes the structure for the * transmit and receive frame descriptors.*/#if (_BYTE_ORDER == _LITTLE_ENDIAN)struct FD_TX_CONTROL_PACKED { UINT32 p_bit:1; UINT32 c_bit:1; UINT32 t_bit:1; UINT32 l_bit:1; UINT32 a_bit:1; UINT32 wa_bit:2; UINT32 reserved_bit:25; }__attribute__((__packed__));#else /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/struct FD_TX_CONTROL_PACKED { UINT32 reserved_bit:25; UINT32 wa_bit:2; UINT32 a_bit:1; UINT32 l_bit:1; UINT32 t_bit:1; UINT32 c_bit:1; UINT32 p_bit:1; }__attribute__((__packed__));#endif /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/typedef struct FD_TX_CONTROL_PACKED FD_TX_CONTROL;#if (_BYTE_ORDER == _LITTLE_ENDIAN)struct FD_TX_FRAMEDATA_PACKED { UINT32 frameDataPtr:31; UINT32 o_bit:1; }__attribute__((__packed__));#else /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/struct FD_TX_FRAMEDATA_PACKED { UINT32 o_bit:1; UINT32 frameDataPtr:31; }__attribute__((__packed__));#endif /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/typedef struct FD_TX_FRAMEDATA_PACKED FD_TX_FRAME_DATA;#if (_BYTE_ORDER == _LITTLE_ENDIAN)struct FD_TX_STATUS_LENGTH_PACKED { UINT32 frameLength:16; UINT32 txCollCnt:4; UINT32 exColl:1; UINT32 txDefer:1; UINT32 paused:1; UINT32 intTx:1; UINT32 underRun:1; UINT32 deferAl:1; UINT32 ncArr:1; UINT32 sqeErr:1; UINT32 lateColl:1; UINT32 txPar:1; UINT32 comp:1; UINT32 txHalted:1; }__attribute__((__packed__));#else /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/struct FD_TX_STATUS_LENGTH_PACKED { UINT32 txHalted:1; UINT32 comp:1; UINT32 txPar:1; UINT32 lateColl:1; UINT32 sqeErr:1; UINT32 ncArr:1; UINT32 deferAl:1; UINT32 underRun:1; UINT32 intTx:1; UINT32 paused:1; UINT32 txDefer:1; UINT32 exColl:1; UINT32 txCollCnt:4; UINT32 frameLength:16; }__attribute__((__packed__));#endif /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/typedef struct FD_TX_STATUS_LENGTH_PACKED FD_TX_STATUS_LENGTH;struct TRANSMIT_FRAME_DESC_PACKED { FD_TX_FRAME_DATA txFrameData; FD_TX_CONTROL txControl; FD_TX_STATUS_LENGTH txStatusLength; struct TRANSMIT_FRAME_DESC_PACKED *nextTxFrameDesc; }__attribute__((__packed__));typedef struct TRANSMIT_FRAME_DESC_PACKED TRANSMIT_FRAME_DESC;#if (_BYTE_ORDER == _LITTLE_ENDIAN)struct FD_RX_FRAME_DATA_PACKED { UINT32 frameDataPtr:31; UINT32 o_bit:1; }__attribute__((__packed__));#else /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/struct FD_RX_FRAME_DATA_PACKED { UINT32 o_bit:1; UINT32 frameDataPtr:31; }__attribute__((__packed__));#endif /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/typedef struct FD_RX_FRAME_DATA_PACKED FD_RX_FRAME_DATA;#if (_BYTE_ORDER == _LITTLE_ENDIAN)struct FD_RX_STATUS_LENGTH_PACKED { UINT32 frameLength:16; UINT32 empty0:3; UINT32 ovMax:1; UINT32 empty1:1; UINT32 ctlRcv:1; UINT32 intRx:1; UINT32 rx10Stat:1; UINT32 alignErr:1; UINT32 crcErr:1; UINT32 overFlow:1; UINT32 longErr:1; UINT32 empty2:1; UINT32 rxPar:1; UINT32 good:1; UINT32 rxHalted:1; }__attribute__((__packed__));#else /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/struct FD_RX_STATUS_LENGTH_PACKED { UINT32 rxHalted:1; UINT32 good:1; UINT32 rxPar:1; UINT32 empty2:1; UINT32 longErr:1; UINT32 overFlow:1; UINT32 crcErr:1; UINT32 alignErr:1; UINT32 rx10Stat:1; UINT32 intRx:1; UINT32 ctlRcv:1; UINT32 empty1:1; UINT32 ovMax:1; UINT32 empty0:3; UINT32 frameLength:16; }__attribute__((__packed__));#endif /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/typedef struct FD_RX_STATUS_LENGTH_PACKED FD_RX_STATUS_LENGTH;struct RECEIVE_FRAME_DESC_PACKED /* receive frame descriptor */ { FD_RX_FRAME_DATA rxFrameData; UINT32 reserved; FD_RX_STATUS_LENGTH rxStatusLength; struct RECEIVE_FRAME_DESC_PACKED *nextRxFrameDesc; }__attribute__((__packed__));typedef struct RECEIVE_FRAME_DESC_PACKED RECEIVE_FRAME_DESC;#if (_BYTE_ORDER == _LITTLE_ENDIAN)struct BDMARXCON_PACKED { UINT32 burstSize:5; UINT32 stop_skipFrame:1; UINT32 memAddrsInc_Dec:1; UINT32 recvFrameIntrEnb:1; UINT32 nullListIntrEnb:1; UINT32 notOwnerIntrEnb:1; UINT32 maxSizeOverIntrEnb:1; UINT32 big_LittleEndian:1; UINT32 wordAlign:2; UINT32 enable:1; UINT32 reset:1; UINT32 buffEmptyIntr:1; UINT32 erlyNotifyIntr:1; UINT32 reserved_0:14; }__attribute__((__packed__));#else /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/struct BDMARXCON_PACKED { UINT32 reserved_0:14; UINT32 erlyNotifyIntr:1; UINT32 buffEmptyIntr:1; UINT32 reset:1; UINT32 enable:1; UINT32 wordAlign:2; UINT32 big_LittleEndian:1; UINT32 maxSizeOverIntrEnb:1; UINT32 notOwnerIntrEnb:1; UINT32 nullListIntrEnb:1; UINT32 recvFrameIntrEnb:1; UINT32 memAddrsInc_Dec:1; UINT32 stop_skipFrame:1; UINT32 burstSize:5; }__attribute__((__packed__));#endif /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/union UNION_BDMARXCON { struct BDMARXCON_PACKED rxCon_reg; UINT32 rxCon_resetval; }__attribute__((__packed__));typedef union UNION_BDMARXCON BDMARXCON;#if (_BYTE_ORDER == _LITTLE_ENDIAN)struct BDMATXCON_PACKED { UINT32 burstSize:5; UINT32 stop_skipFrame:1; UINT32 reserved_0:1; UINT32 sendCntrlPacketIntrEnb:1; UINT32 nullListIntrEnb:1; UINT32 notOwnerIntrEnb:1; UINT32 buffEmptyIntrEnb:1; UINT32 macTxStartLevel:3; UINT32 enable:1; UINT32 reset:1; UINT32 reserved_1:16; }__attribute__((__packed__));#else /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/struct BDMATXCON_PACKED { UINT32 reserved_1:16; UINT32 reset:1; UINT32 enable:1; UINT32 macTxStartLevel:3; UINT32 buffEmptyIntrEnb:1; UINT32 notOwnerIntrEnb:1; UINT32 nullListIntrEnb:1; UINT32 sendCntrlPacketIntrEnb:1; UINT32 reserved_0:1; UINT32 stop_skipFrame:1; UINT32 burstSize:5; }__attribute__((__packed__));#endif /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/union UNION_BDMATXCON { struct BDMATXCON_PACKED txCon_reg; UINT32 txCon_resetval; }__attribute__((__packed__));typedef union UNION_BDMATXCON BDMATXCON;#if (_BYTE_ORDER == _LITTLE_ENDIAN)struct BDMARXPTR_PACKED { UINT32 bdmaRxPointer:27; /* extra bit holds non-cache region */ UINT32 reserved:5; }__attribute__((__packed__));#else /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/struct BDMARXPTR_PACKED { UINT32 reserved:5; UINT32 bdmaRxPointer:27; /* extra bit holds non-cache region */ }__attribute__((__packed__));#endif /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/union UNION_BDMARXPTR { struct BDMARXPTR_PACKED rxPtr_reg; UINT32 rxPtr_resetval; }__attribute__((__packed__));typedef union UNION_BDMARXPTR BDMARXPTR;#if (_BYTE_ORDER == _LITTLE_ENDIAN)struct BDMATXPTR_PACKED { UINT32 bdmaTxPointer:27; /* extra bit holds non-cache region */ UINT32 reserved:5; }__attribute__((__packed__));#else /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/struct BDMATXPTR_PACKED { UINT32 reserved:5; UINT32 bdmaTxPointer:27; /* extra bit holds non-cache region */ }__attribute__((__packed__));#endif /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/union UNION_BDMATXPTR { struct BDMATXPTR_PACKED txPtr_reg; UINT32 txPtr_resetval; }__attribute__((__packed__));typedef union UNION_BDMATXPTR BDMATXPTR;#if (_BYTE_ORDER == _LITTLE_ENDIAN)struct BDMARXLSZ_PACKED { UINT32 bdmaRxMaxSize:16; UINT32 bdmaRxFrameLength:16; }__attribute__((__packed__));#else /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/struct BDMARXLSZ_PACKED { UINT32 bdmaRxFrameLength:16; UINT32 bdmaRxMaxSize:16; }__attribute__((__packed__));#endif /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/union UNION_BDMARXLSZ { struct BDMARXLSZ_PACKED rxLsz_reg; UINT32 rxLsz_resetval; }__attribute__((__packed__));typedef union UNION_BDMARXLSZ BDMARXLSZ;#if (_BYTE_ORDER == _LITTLE_ENDIAN)struct BDMASTAT_PACKED { UINT32 bdmaRxDoneEveryRxFrame:1;?? 快捷鍵說明
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