UINT32 bdmaRxNullList:1;    UINT32 bdmaRxNotOwner:1;    UINT32 bdmaRxMaxSizeOver:1;    UINT32 bdmaRxBuffEmpty:1;    UINT32 bdmaRxEarlyNotify:1;    UINT32 bdmaRxReserved:1;    UINT32 bdmaRxOneMoreFrame:1;    UINT32 bdmaRxNumofFrames_Buff:8;    UINT32 bdmaTxCompleteToSendCntrlPacket:1;    UINT32 bdmaTxNullList:1;    UINT32 bdmaTxNotOwner:1;    UINT32 bdmaTxReserved_0:1;    UINT32 bdmaTxBuffEmpty:1;    UINT32 bdmaTxReserved_1:11;    }__attribute__((__packed__));#else /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/struct BDMASTAT_PACKED    {    UINT32 bdmaTxReserved_1:11;    UINT32 bdmaTxBuffEmpty:1;    UINT32 bdmaTxReserved_0:1;    UINT32 bdmaTxNotOwner:1;    UINT32 bdmaTxNullList:1;    UINT32 bdmaTxCompleteToSendCntrlPacket:1;    UINT32 bdmaRxNumofFrames_Buff:8;    UINT32 bdmaRxOneMoreFrame:1;    UINT32 bdmaRxReserved:1;    UINT32 bdmaRxEarlyNotify:1;    UINT32 bdmaRxBuffEmpty:1;    UINT32 bdmaRxMaxSizeOver:1;    UINT32 bdmaRxNotOwner:1;    UINT32 bdmaRxNullList:1;    UINT32 bdmaRxDoneEveryRxFrame:1;    }__attribute__((__packed__));#endif /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/union UNION_BDMASTAT    {        struct BDMASTAT_PACKED    stat_reg;        UINT32 stat_resetval;    }__attribute__((__packed__));typedef union UNION_BDMASTAT BDMASTAT;#if (_BYTE_ORDER == _LITTLE_ENDIAN)struct MACCON_PACKED    {    UINT32 haltRequest:1;    UINT32 haltImm:1;    UINT32 swReset:1;    UINT32 fullDup:1;    UINT32 macLoop:1;    UINT32 reserved_0:1;    UINT32 mii_off:1;    UINT32 loop10:1;    UINT32 reserved_1:2;    UINT32 missRoll:1;    UINT32 reserved_2:1;    UINT32 mdc_off:1;    UINT32 enMissRoll:1;    UINT32 reserved_3:1;    UINT32 linkStatus:1;    UINT32 reserved_4:16;    }__attribute__((__packed__));#else /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/struct MACCON_PACKED    {    UINT32 reserved_4:16;    UINT32 linkStatus:1;    UINT32 reserved_3:1;    UINT32 enMissRoll:1;    UINT32 mdc_off:1;    UINT32 reserved_2:1;    UINT32 missRoll:1;    UINT32 reserved_1:2;    UINT32 loop10:1;    UINT32 mii_off:1;    UINT32 reserved_0:1;    UINT32 macLoop:1;    UINT32 fullDup:1;    UINT32 swReset:1;    UINT32 haltImm:1;    UINT32 haltRequest:1;    }__attribute__((__packed__));#endif /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/union UNION_MACCON    {        struct MACCON_PACKED    macCon_reg;        UINT32 macCon_resetval;    }__attribute__((__packed__));typedef union UNION_MACCON MACCON;#if (_BYTE_ORDER == _LITTLE_ENDIAN)struct CAMCON_PACKED    {    UINT32 stationAccept:1;    UINT32 groupAccept:1;    UINT32 broadcastAccept:1;    UINT32 negCam:1;    UINT32 cmpEnable:1;    UINT32 reserved_0:27;    }__attribute__((__packed__));#else /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/struct CAMCON_PACKED    {    UINT32 reserved_0:27;    UINT32 cmpEnable:1;    UINT32 negCam:1;    UINT32 broadcastAccept:1;    UINT32 groupAccept:1;    UINT32 stationAccept:1;    }__attribute__((__packed__));#endif /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/union UNION_CAMCON    {        struct CAMCON_PACKED    camCon_reg;        UINT32 camCon_resetval;    }__attribute__((__packed__));typedef union UNION_CAMCON CAMCON;#if (_BYTE_ORDER == _LITTLE_ENDIAN)struct MACTXCON_PACKED    {    UINT32 transmitEnable:1;    UINT32 transmitHaltReq:1;    UINT32 suppressPadding:1;    UINT32 suppressCRC:1;    UINT32 fastBackOff:1;    UINT32 noDefer:1;    UINT32 sendPause:1;    UINT32 sqeTestModeEnable:1;    UINT32 enableUnderRun:1;    UINT32 enableDeferral:1;    UINT32 enableNoCarrier:1;    UINT32 enableExcessCollision:1;    UINT32 enableLateCollison:1;    UINT32 enableTxParity:1;    UINT32 enableCompletion:1;    UINT32 reserved_0:17;    }__attribute__((__packed__));#else /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/struct MACTXCON_PACKED    {    UINT32 reserved_0:17;    UINT32 enableCompletion:1;    UINT32 enableTxParity:1;    UINT32 enableLateCollison:1;    UINT32 enableExcessCollision:1;    UINT32 enableNoCarrier:1;    UINT32 enableDeferral:1;    UINT32 enableUnderRun:1;    UINT32 sqeTestModeEnable:1;    UINT32 sendPause:1;    UINT32 noDefer:1;    UINT32 fastBackOff:1;    UINT32 suppressCRC:1;    UINT32 suppressPadding:1;    UINT32 transmitHaltReq:1;    UINT32 transmitEnable:1;    }__attribute__((__packed__));#endif /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/union UNION_MACTXCON    {        struct MACTXCON_PACKED    macTxCon_reg;        UINT32 macTxCon_resetval;    }__attribute__((__packed__));typedef union UNION_MACTXCON MACTXCON;#if (_BYTE_ORDER == _LITTLE_ENDIAN)struct MACTXSTAT_PACKED    {    UINT32 transmitCollCount:4;    UINT32 excessiveCollision:1;    UINT32 transmitDeferred:1;    UINT32 paused:1;    UINT32 intrOnTransmit:1;    UINT32 underRun:1;    UINT32 deferral:1;    UINT32 noCarrier:1;    UINT32 sqe:1;    UINT32 lateCollision:1;    UINT32 transmitParityError:1;    UINT32 completion:1;    UINT32 transmissionHalted:1;    UINT32 reserved_0:16;    }__attribute__((__packed__));#else /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/struct MACTXSTAT_PACKED    {    UINT32 reserved_0:16;    UINT32 transmissionHalted:1;    UINT32 completion:1;    UINT32 transmitParityError:1;    UINT32 lateCollision:1;    UINT32 sqe:1;    UINT32 noCarrier:1;    UINT32 deferral:1;    UINT32 underRun:1;    UINT32 intrOnTransmit:1;    UINT32 paused:1;    UINT32 transmitDeferred:1;    UINT32 excessiveCollision:1;    UINT32 transmitCollCount:4;    }__attribute__((__packed__));#endif /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/union UNION_MACTXSTAT    {        struct MACTXSTAT_PACKED    macTxStat_reg;        UINT32 macTxStat_resetval;    }__attribute__((__packed__));typedef union UNION_MACTXSTAT MACTXSTAT;#if (_BYTE_ORDER == _LITTLE_ENDIAN)struct MACRXCON_PACKED    {    UINT32 receiveEnable:1;    UINT32 receiveHaltReq:1;    UINT32 longEnable:1;    UINT32 shortEnable:1;    UINT32 stripCRCVal:1;    UINT32 passCtrlPacket:1;    UINT32 ignoreCRCValue:1;    UINT32 reserved_0:1;    UINT32 enableAlignment:1;    UINT32 enableCRCError:1;    UINT32 enableOverFlow:1;    UINT32 enableLongError:1;    UINT32 reserved_1:1;    UINT32 enableReceiveParity:1;    UINT32 enableGood:1;    UINT32 reserved_2:17;    }__attribute__((__packed__));#else /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/struct MACRXCON_PACKED    {    UINT32 reserved_2:17;    UINT32 enableGood:1;    UINT32 enableReceiveParity:1;    UINT32 reserved_1:1;    UINT32 enableLongError:1;    UINT32 enableOverFlow:1;    UINT32 enableCRCError:1;    UINT32 enableAlignment:1;    UINT32 reserved_0:1;    UINT32 ignoreCRCValue:1;    UINT32 passCtrlPacket:1;    UINT32 stripCRCVal:1;    UINT32 shortEnable:1;    UINT32 longEnable:1;    UINT32 receiveHaltReq:1;    UINT32 receiveEnable:1;    }__attribute__((__packed__));#endif /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/union UNION_MACRXCON    {        struct MACRXCON_PACKED    macRxCon_reg;        UINT32 macRxCon_resetval;    }__attribute__((__packed__));typedef union UNION_MACRXCON MACRXCON;#if (_BYTE_ORDER == _LITTLE_ENDIAN)struct MACRXSTAT_PACKED    {    UINT32 reserved_0:5;    UINT32 ctrlFrameReceived:1;    UINT32 intrOnReceive:1;    UINT32 receive10MbStatus:1;    UINT32 alignmentError:1;    UINT32 crcError:1;    UINT32 overflowError:1;    UINT32 longError:1;    UINT32 reserved_1:1;    UINT32 receiveParityError:1;    UINT32 goodReceived:1;    UINT32 receptionHalted:1;    UINT32 reserved_2:16;    }__attribute__((__packed__));#else /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/struct MACRXSTAT_PACKED    {    UINT32 reserved_2:16;    UINT32 receptionHalted:1;    UINT32 goodReceived:1;    UINT32 receiveParityError:1;    UINT32 reserved_1:1;    UINT32 longError:1;    UINT32 overflowError:1;    UINT32 crcError:1;    UINT32 alignmentError:1;    UINT32 receive10MbStatus:1;    UINT32 intrOnReceive:1;    UINT32 ctrlFrameReceived:1;    UINT32 reserved_0:5;    }__attribute__((__packed__));#endif /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/union UNION_MACRXSTAT    {        struct MACRXSTAT_PACKED    macRxCon_reg;        UINT32 macRxCon_resetval;    }__attribute__((__packed__));typedef union UNION_MACRXSTAT MACRXSTAT;#if (_BYTE_ORDER == _LITTLE_ENDIAN)struct STACON_PACKED    {    UINT32 phyRegisterAddr:5;    UINT32 phyAddr:5;    UINT32 write:1;    UINT32 busy:1;    UINT32 preambleSuppress:1;    UINT32 mdc_Clockrating:3;    UINT32 reserved_0:16;    }__attribute__((__packed__));#else /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/struct STACON_PACKED    {    UINT32 reserved_0:16;    UINT32 mdc_Clockrating:3;    UINT32 preambleSuppress:1;    UINT32 busy:1;    UINT32 write:1;    UINT32 phyAddr:5;    UINT32 phyRegisterAddr:5;    }__attribute__((__packed__));#endif /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/union UNION_STACON    {        struct STACON_PACKED    staCon_reg;        UINT32 staCon_resetval;    }__attribute__((__packed__));typedef union UNION_STACON STACON;#if (_BYTE_ORDER == _LITTLE_ENDIAN)struct CAMEN_PACKED    {    UINT32 camEnable:21;    UINT32 reserved_0:11;    }__attribute__((__packed__));#else /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/struct CAMEN_PACKED    {    UINT32 reserved_0:11;    UINT32 camEnable:21;    }__attribute__((__packed__));#endif /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/union UNION_CAMEN    {        struct CAMEN_PACKED    camen_reg;        UINT32 camen_resetval;    }__attribute__((__packed__));typedef union UNION_CAMEN CAMEN;#if (_BYTE_ORDER == _LITTLE_ENDIAN)struct EMISSCNT_PACKED    {    UINT32 alignmentErrorCount:16;    UINT32 reserved_0:16;    }__attribute__((__packed__));#else /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/struct EMISSCNT_PACKED    {    UINT32 reserved_0:16;    UINT32 alignmentErrorCount:16;    }__attribute__((__packed__));#endif /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/union UNION_EMISSCNT    {    struct EMISSCNT_PACKED    emisscnt_reg;    UINT32 emisscnt_resetval;    }__attribute__((__packed__));typedef union UNION_EMISSCNT EMISSCNT;typedef struct etherStatistics{    /* Receive statistics counters from */    UINT32 rxGood;    UINT32 rxBad;    UINT32 rxOvMaxSize;    UINT32 rxCtlRecd;    UINT32 rx10Stat;    UINT32 rxAlignErr;    UINT32 rxCRCErr;    UINT32 rxOverflowErr;    UINT32 rxLongErr;    UINT32 rxParErr;    UINT32 rxHalted;    /* Transmit statistics counters */    UINT32 txGood;    UINT32 txUnderErr;    UINT32 txExCollErr;