UINT32 txDeferredErr;    UINT32 txPaused;    UINT32 txDeferErr;    UINT32 txNCarrErr;    UINT32 txSQE;    UINT32 txLateCollErr;    UINT32 txParErr;    UINT32 txHalted;} ETHER_STATISTICS;/**********BDMA control registers **************/#define AT91C_BDMATXCON         (ASIC_BASE+0x9000)#define AT91C_BDMARXCON         (ASIC_BASE+0x9004)#define AT91C_BDMATXPTR         (ASIC_BASE+0x9008)#define AT91C_BDMARXPTR         (ASIC_BASE+0x900C)#define AT91C_BDMARXLSZ         (ASIC_BASE+0x9010)#define AT91C_BDMASTAT        (ASIC_BASE+0x9014)/****** Content Addressable Memory  registers ******/#define AT91C_CAM_BASE    (ASIC_BASE+0x9100)#define AT91C_CAM0    (ASIC_BASE+0x9100)#define AT91C_CAM1     (ASIC_BASE+0x9106)#define AT91C_CAM2     (ASIC_BASE+0x910C)#define AT91C_CAM3    (ASIC_BASE+0x9112)#define AT91C_CAM4     (ASIC_BASE+0x9118)#define AT91C_CAM5     (ASIC_BASE+0x911e)#define AT91C_CAM6     (ASIC_BASE+0x9124)#define AT91C_CAM7     (ASIC_BASE+0x912a)#define AT91C_CAM8     (ASIC_BASE+0x9130)#define AT91C_CAM9     (ASIC_BASE+0x9136)#define AT91C_CAM10     (ASIC_BASE+0x913c)#define AT91C_CAM11     (ASIC_BASE+0x9142)#define AT91C_CAM12    (ASIC_BASE+0x9148)#define AT91C_CAM13    (ASIC_BASE+0x914e)#define AT91C_CAM14     (ASIC_BASE+0x9154)#define AT91C_CAM15     (ASIC_BASE+0x915a)#define AT91C_CAM16     (ASIC_BASE+0x9160)#define AT91C_CAM17     (ASIC_BASE+0x9166)#define AT91C_CAM18     (ASIC_BASE+0x916c)#define AT91C_CAM19     (ASIC_BASE+0x9172)#define AT91C_CAM20     (ASIC_BASE+0x9178)/*******Buffer registers for debug pupose ***/    /* to be removed after driver development */#define AT91C_BDMATXBUF     (ASIC_BASE+0x9200)#define AT91C_BDMARXBUF    (ASIC_BASE+0x9800)/***********MAC control registers**************/#define AT91C_MACCON             (ASIC_BASE+0xA000)#define AT91C_CAMCON             (ASIC_BASE+0xA004)#define AT91C_MACTXCON           (ASIC_BASE+0xA008)#define AT91C_MACTXSTAT          (ASIC_BASE+0xA00C)#define AT91C_MACRXCON           (ASIC_BASE+0xA010)#define AT91C_MACRXSTAT          (ASIC_BASE+0xA014)#define AT91C_STADATA            (ASIC_BASE+0xA018)#define AT91C_STACON             (ASIC_BASE+0xA01C)#define AT91C_CAMEN              (ASIC_BASE+0xA028)#define AT91C_EMISSCNT           (ASIC_BASE+0xA03C)#define AT91C_EPZCNT             (ASIC_BASE+0xA040)#define AT91C_ERMPZCNT           (ASIC_BASE+0xA044)#define AT91C_ETXSTAT            (ASIC_BASE+0x9040)#endiftypedef struct emacStatistics{	UINT32 txFRA;/*	UINT16 txSCOL;		UINT16 txMCOL;*/	UINT32 rxOK;/*		UINT8 rxSEQE;		UINT8 rxALE;	UINT16 txDTE;	UINT8 txLCOL;	UINT8 txECOL;	UINT8 txCSE;	UINT8 txTUE;	UINT8 rxCDE;	UINT8 rxELR;	UINT8 rxRJB;	UINT8 rxUSF;	UINT8 rxSQEE;	UINT16 rxDRFC; */	/*reserved*/} EMAC_STATISTICS;  /* ownerShip_bit */#define OWNED_BY_CPU 1#define OWNED_BY_DMA 0/*注意大端小端問題，目前是小端--低對低*//*位操作，前面低地址，后面是高*/#if (_BYTE_ORDER == _LITTLE_ENDIAN)struct WORD0{	UINT32 ownerShip:1;	UINT32 wrap:1;	UINT32 baseAddrRecBuf:30;}__attribute__((__packed__));#else /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/struct WORD0{	UINT32 baseAddrRecBuf:30;	UINT32 wrap:1;	UINT32 ownerShip:1;}__attribute__((__packed__));#endif /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/#if (_BYTE_ORDER == _LITTLE_ENDIAN)struct WORD1{	UINT32 frameLength :11;		/*including FCS */	UINT32 reserved_1 :12; 			/* written to 0 */	UINT32 localAddrMatch_4 :1;	/*Specific address 4 match*/	UINT32 localAddrMatch_3 :1;	/*Specific address 3 match*/	UINT32 localAddrMatch_2 :1;	/*Specific address 2 match*/	UINT32 localAddrMatch_1 :1;	/*Specific address 1 match*/	UINT32 reserved_0 :1;		UINT32 optExtAddr :1;	UINT32 unicastHashMatch :1;	UINT32 multicastHashMatch :1;		UINT32 broadcastAddrDetected :1;}__attribute__((__packed__));#else /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/struct WORD1{	UINT32 broadcastAddrDetected :1;	UINT32 multicastHashMatch :1;	UINT32 unicastHashMatch :1;	UINT32 optExtAddr :1;	UINT32 reserved_0 :1;			UINT32 localAddrMatch_1 :1;	/*Specific address 1 match*/	UINT32 localAddrMatch_2 :1;	/*Specific address 2 match*/	UINT32 localAddrMatch_3 :1;	/*Specific address 3 match*/	UINT32 localAddrMatch_4 :1;	/*Specific address 4 match*/	UINT32 reserved_1 :12; 			/* written to 0 */	UINT32 frameLength :11;		/*including FCS */	}__attribute__((__packed__));#endif /*(_BYTE_ORDER == _LITTLE_ENDIAN)*//*Received Buffer Descriptor Words*/typedef struct recBufDescWords{	struct WORD0  w0;	struct WORD1  w1;	}RECEIVE_BUF_DESC;/*typedef struct transBufDesc{	UINT32 transBufPtr;	struct transBufDesc* nextTxBufDesc;}TRANSMIT_BUF_DESC;*/struct transFd{	UINT32 transBufPtr;	UINT32 length;};typedef struct transBufDesc{	struct transFd transBufFd[64];	UINT32 head;	UINT32 tail;}TRANSMIT_BUF_DESC;/* ========== Register definition for EMAC peripheral ==========  */#define AT91C_EMAC_RSR   	0xFFFBC020       /* (EMAC) Receive Status Register */#define AT91C_EMAC_MAN   	0xFFFBC034       /* (EMAC) PHY Maintenance Register */#define AT91C_EMAC_HSH   	0xFFFBC090       /* (EMAC) Hash Address High[63:32] */#define AT91C_EMAC_MCOL  	0xFFFBC048       /* (EMAC) Multiple Collision Frame Register */#define AT91C_EMAC_IER   	0xFFFBC028       /* (EMAC) Interrupt Enable Register */#define AT91C_EMAC_SA2H  	0xFFFBC0A4       /* (EMAC) Specific Address 2 High, Last 2 bytes */#define AT91C_EMAC_HSL   	0xFFFBC094       /* (EMAC) Hash Address Low[31:0] */#define AT91C_EMAC_LCOL  	0xFFFBC05C       /* (EMAC) Late Collision Register */#define AT91C_EMAC_OK    	0xFFFBC04C       /* (EMAC) Frames Received OK Register */#define AT91C_EMAC_CFG   	0xFFFBC004       /* (EMAC) Network Configuration Register */#define AT91C_EMAC_SA3L  	0xFFFBC0A8       /* (EMAC) Specific Address 3 Low, First 4 bytes */#define AT91C_EMAC_SEQE  	0xFFFBC050       /* (EMAC) Frame Check Sequence Error Register */#define AT91C_EMAC_ECOL  	0xFFFBC060       /* (EMAC) Excessive Collision Register */#define AT91C_EMAC_ELR   	0xFFFBC070       /* (EMAC) Excessive Length Error Register */#define AT91C_EMAC_SR    	0xFFFBC008       /* (EMAC) Network Status Register */#define AT91C_EMAC_RBQP  	0xFFFBC018       /* (EMAC) Receive Buffer Queue Pointer */#define AT91C_EMAC_CSE   	0xFFFBC064       /* (EMAC) Carrier Sense Error Register */#define AT91C_EMAC_RJB   	0xFFFBC074       /* (EMAC) Receive Jabber Register */#define AT91C_EMAC_USF   	0xFFFBC078       /* (EMAC) Undersize Frame Register */#define AT91C_EMAC_IDR   	0xFFFBC02C       /* (EMAC) Interrupt Disable Register */#define AT91C_EMAC_SA1L  	0xFFFBC098       /* (EMAC) Specific Address 1 Low, First 4 bytes */#define AT91C_EMAC_IMR   	0xFFFBC030       /* (EMAC) Interrupt Mask Register */#define AT91C_EMAC_FRA   	0xFFFBC040       /* (EMAC) Frames Transmitted OK Register */#define AT91C_EMAC_SA3H  	0xFFFBC0AC       /* (EMAC) Specific Address 3 High, Last 2 bytes */#define AT91C_EMAC_SA1H  	0xFFFBC09C       /* (EMAC) Specific Address 1 High, Last 2 bytes */#define AT91C_EMAC_SCOL  	0xFFFBC044       /* (EMAC) Single Collision Frame Register */#define AT91C_EMAC_ALE   	0xFFFBC054       /* (EMAC) Alignment Error Register */#define AT91C_EMAC_TAR   	0xFFFBC00C       /* (EMAC) Transmit Address Register */#define AT91C_EMAC_SA4L  	0xFFFBC0B0       /* (EMAC) Specific Address 4 Low, First 4 bytes */#define AT91C_EMAC_SA2L  	0xFFFBC0A0       /* (EMAC) Specific Address 2 Low, First 4 bytes */#define AT91C_EMAC_TUE   	0xFFFBC068       /* (EMAC) Transmit Underrun Error Register */#define AT91C_EMAC_DTE   	0xFFFBC058       /* (EMAC) Deferred Transmission Frame Register */#define AT91C_EMAC_TCR   	0xFFFBC010       /* (EMAC) Transmit Control Register */#define AT91C_EMAC_CTL   	0xFFFBC000       /* (EMAC) Network Control Register */#define AT91C_EMAC_SA4H  	0xFFFBC0B4       /* (EMAC) Specific Address 4 High, Last 2 bytes */#define AT91C_EMAC_CDE   	0xFFFBC06C       /* (EMAC) Code Error Register */#define AT91C_EMAC_SQEE  	0xFFFBC07C       /* (EMAC) SQE Test Error Register */#define AT91C_EMAC_TSR   	0xFFFBC014       /* (EMAC) Transmit Status Register */#define AT91C_EMAC_DRFC  	0xFFFBC080       /* (EMAC) Discarded RX Frame Register */#define AT91C_EMAC_ISR		0xFFFBC024       /* (EMAC) Interrupt status Register */		/* -------- EMAC_CTL : (EMAC Offset: 0x0)  -------- */#define AT91C_EMAC_LB         ((unsigned int) 0x1 <<  0) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */#define AT91C_EMAC_LBL        ((unsigned int) 0x1 <<  1) /* (EMAC) Loopback local. */#define AT91C_EMAC_RE         ((unsigned int) 0x1 <<  2) /* (EMAC) Receive enable. */#define AT91C_EMAC_TE         ((unsigned int) 0x1 <<  3) /* (EMAC) Transmit enable. */#define AT91C_EMAC_MPE        ((unsigned int) 0x1 <<  4) /* (EMAC) Management port enable. */#define AT91C_EMAC_CSR        ((unsigned int) 0x1 <<  5) /* (EMAC) Clear statistics registers. */#define AT91C_EMAC_ICSR        ((unsigned int) 0x1 <<  6) /* (EMAC) Increment statistics registers. */#define AT91C_EMAC_WES        ((unsigned int) 0x1 <<  7) /* (EMAC) Write enable for statistics registers. */#define AT91C_EMAC_BP         ((unsigned int) 0x1 <<  8) /* (EMAC) Back pressure. *//* -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- */#define AT91C_EMAC_SPD        ((unsigned int) 0x1 <<  0) /* (EMAC) Speed. */#define AT91C_EMAC_FD          ((unsigned int) 0x1 <<  1) /* (EMAC) Full duplex. */ #define AT91C_EMAC_BR          ((unsigned int) 0x1 <<  2) /* (EMAC) Bit rate. */#define AT91C_EMAC_CAF        ((unsigned int) 0x1 <<  4) /* (EMAC) Copy all frames. */#define AT91C_EMAC_NBC        ((unsigned int) 0x1 <<  5) /* (EMAC) No broadcast. */#define AT91C_EMAC_MTI        ((unsigned int) 0x1 <<  6) /* (EMAC) Multicast hash enable */#define AT91C_EMAC_UNI        ((unsigned int) 0x1 <<  7) /* (EMAC) Unicast hash enable. */#define AT91C_EMAC_BIG        ((unsigned int) 0x1 <<  8) /* (EMAC) Receive 1522 bytes. */#define AT91C_EMAC_EAE        ((unsigned int) 0x1 <<  9) /* (EMAC) External address match enable. */#define AT91C_EMAC_CLK         ((unsigned int) 0x3 << 10) /* (EMAC) */#define 	AT91C_EMAC_CLK_HCLK_8               ((unsigned int) 0x0 << 10) /* (EMAC) HCLK divided by 8 */#define 	AT91C_EMAC_CLK_HCLK_16              ((unsigned int) 0x1 << 10) /* (EMAC) HCLK divided by 16 */#define 	AT91C_EMAC_CLK_HCLK_32              ((unsigned int) 0x2 << 10) /* (EMAC) HCLK divided by 32 */#define 	AT91C_EMAC_CLK_HCLK_64              ((unsigned int) 0x3 << 10) /* (EMAC) HCLK divided by 64 */#define AT91C_EMAC_RTY        ((unsigned int) 0x1 << 12) /* (EMAC)  */#define AT91C_EMAC_RMII       ((unsigned int) 0x1 << 13) /* (EMAC) *//* -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register --------  */#define AT91C_EMAC_MDIO       ((unsigned int) 0x1 <<  1) /* (EMAC) */#define AT91C_EMAC_IDLE       ((unsigned int) 0x1 <<  2) /* (EMAC) *//* -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- */ #define AT91C_EMAC_LEN        ((unsigned int) 0x7FF <<  0) /* (EMAC) */#define AT91C_EMAC_NCRC       ((unsigned int) 0x1 << 15) /* (EMAC) *//* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register --------  */#define AT91C_EMAC_OVR        ((unsigned int) 0x1 <<  0) /* (EMAC) */#define AT91C_EMAC_COL        ((unsigned int) 0x1 <<  1) /* (EMAC)  */#define AT91C_EMAC_RLE        ((unsigned int) 0x1 <<  2) /* (EMAC)  */#define AT91C_EMAC_TXIDLE     ((unsigned int) 0x1 <<  3) /* (EMAC)  */#define AT91C_EMAC_BNQ        ((unsigned int) 0x1 <<  4) /* (EMAC)  */#define AT91C_EMAC_COMP       ((unsigned int) 0x1 <<  5) /* (EMAC)  */#define AT91C_EMAC_UND        ((unsigned int) 0x1 <<  6) /* (EMAC)  *//* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------  */#define AT91C_EMAC_BNA        ((unsigned int) 0x1 <<  0) /* (EMAC)  */#define AT91C_EMAC_REC        ((unsigned int) 0x1 <<  1) /* (EMAC)  *//* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */#define AT91C_EMAC_DONE       ((unsigned int) 0x1 <<  0) /* (EMAC)  */#define AT91C_EMAC_RCOM       ((unsigned int) 0x1 <<  1) /* (EMAC)  */#define AT91C_EMAC_RBNA       ((unsigned int) 0x1 <<  2) /* (EMAC)  */#define AT91C_EMAC_TOVR       ((unsigned int) 0x1 <<  3) /* (EMAC)  */#define AT91C_EMAC_TUND       ((unsigned int) 0x1 <<  4) /* (EMAC)  */#define AT91C_EMAC_RTRY       ((unsigned int) 0x1 <<  5) /* (EMAC)  */#define AT91C_EMAC_TBRE       ((unsigned int) 0x1 <<  6) /* (EMAC)  */#define AT91C_EMAC_TCOM       ((unsigned int) 0x1 <<  7) /* (EMAC)  */#define AT91C_EMAC_TIDLE      ((unsigned int) 0x1 <<  8) /* (EMAC)  */#define AT91C_EMAC_LINK       ((unsigned int) 0x1 <<  9) /* (EMAC)  */#define AT91C_EMAC_ROVR       ((unsigned int) 0x1 << 10) /* (EMAC)  */#define AT91C_EMAC_ABT      ((unsigned int) 0x1 << 11) /* (EMAC)  *//* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- *//* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- *//* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- *//* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */#define AT91C_EMAC_DATA       ((unsigned int) 0xFFFF <<  0) /* (EMAC)  */#define AT91C_EMAC_CODE       ((unsigned int) 0x2 << 16) /* (EMAC)  */#define AT91C_EMAC_RD         ((unsigned int) 0x2 << 28) /* (EMAC)  */#define AT91C_EMAC_WR         ((unsigned int) 0x1 << 28) /* (EMAC)  */#define AT91C_EMAC_HIGH       ((unsigned int) 0x1 << 30) /* (EMAC)  *//* EMAC interrupt level */#define AT91C_INT_LVL_EMAC			24 /*EMAC interrupt*//* Configuration items */#define AT91CEND_DEV_NAME       "atm"#define AT91CEND_DEV_NAME_LEN   4#define ENET_HDR_REAL_SIZ          14#define AT91C_END_ALIGN         0#define END_BUFSIZ     (ETHERMTU + ENET_HDR_REAL_SIZ + 6 + AT91C_END_ALIGN)#define END_FRAME_LEN 	1514 /* The definition of the driver control structure */typedef struct end_device    {    END_OBJ           end;             /* The class we inherit from. */    int               unit;            /* unit number */    int 		  ivecEMAC;		/*EMAC interrupt vector*/	    long              flags;           /* Our local flags. */    UCHAR             enetAddr[6];     /* ethernet address */    CACHE_FUNCS      *cacheFuncs;      /* cache function pointers */    UCHAR             netSpeed;        /* 10 or 100 */    UCHAR             duplexMode;      /* HDX = 0. FDX = 1 */    UCHAR             autoNeg;         /* 1 = autoneg enabled */    BOOL              fdInitialized;   /* Set to TRUE after FD allocation */    EMAC_STATISTICS  statistics;      /* EMAC statistics counters */	   /* Array for storing addresses Max = 4 */    UINT32            addrList[6];    UINT32            mcastAddrCount; /* Number of valid multicast addresses */    BOOL              loaded;          /* interface has been loaded */    BOOL              rxHandling;    BOOL              resetting;    RECEIVE_BUF_DESC    *pRxBufDesc;    TRANSMIT_BUF_DESC *pTxBufDesc;	    UCHAR *  pTxBuf;    UCHAR tail;		        END_ERR           lastError;      /* Last error passed to muxError */    } END_DEVICE;#ifdef __cplusplus}#endif#endif /* __INCsngks32cEndh */