/* line_rate_bw_in_rx.uc
 *
 *
 *
 * NOTE: THIS IS NOT A PERFORMANCE BENCHMARK!!!! IT IS JUST TO CHECK IF THE
 *       HARDWARE IS ABLE TO HANDLE DATA AT THE LINERATE THAT IS BEING
 *       PUMPED INTO THE SYSTEM
 *
 *---------------------------------------------------------------------------
 *                                                                      
 *                  I N T E L   P R O P R I E T A R Y                   
 *                                                                      
 *     COPYRIGHT (c)  2002 BY  INTEL  CORPORATION.  ALL RIGHTS          
 *     RESERVED.   NO  PART  OF THIS PROGRAM  OR  PUBLICATION  MAY      
 *     BE  REPRODUCED,   TRANSMITTED,   TRANSCRIBED,   STORED  IN  A    
 *     RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER    
 *     LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,    
 *     MAGNETIC,  OPTICAL,  CHEMICAL, MANUAL, OR OTHERWISE,  WITHOUT    
 *     THE PRIOR WRITTEN PERMISSION OF :                                
 *                                                                      
 *                        INTEL  CORPORATION                            
 *                                                                     
 *                     2200 MISSION COLLEGE BLVD                        
 *                                                                      
 *               SANTA  CLARA,  CALIFORNIA  95052-8119                  
 *                                                                      
 *---------------------------------------------------------------------------
 *
 *
 *  system: IXDP2400
 *  subsystem: DIAG
 *  author: dalsraja, November 11, 2002
 *  revisions:
 * 
 * 
 * --------------------------------------------------------------------------
 */

#include "line_rate_bw.h"

#define BUFFER_ADDR_MASK				0xFFFFFF

#define NEXT_CTX_SIGNAL_NUM				EG_SAME_ME_SIG_NUM
#define NEXT_CTX_SIG_DATA				((1 << 7) | (NEXT_CTX_SIGNAL_NUM << 3))

.reg cur_me cur_ctx
.reg ring_num
.reg TBuf_Base @tbuf_element
.reg sram_channel_number t0
.reg @sramDescBase @dramPacketBase @mask_qa
.reg buf_addr buf_offset byte_count
.reg base_element_for_port cur_tbuf_elem
.reg tbuf_count @tx_count TxSequenceAddr
.reg $TxControlWord0 $TxControlWord1

.sig scratch_sig sram_sig dram_sig msf_sig
.sig next_ctx_sig inter_me_sig

.xfer_order $TxControlWord0 $TxControlWord1

.addr next_ctx_sig EG_SAME_ME_SIG_NUM
.addr inter_me_sig EG_INTER_ME_SIG_NUM


// *****************************************
// Get current ME and ctx info
// *****************************************
.begin
	.reg temp
	local_csr_rd[ACTIVE_CTX_STS]
	immed[temp, 0]
	alu[cur_me, 0x1F, AND, temp, >>3]	// Extract the current ME number
	alu[cur_ctx, 0x7, AND, temp]		// Extract the current context number
.end

	.if (cur_me > 4)
		ctx_arb[kill]
	.endif

	immed[TxSequenceAddr, TX_SEQUENCE_0]
	alu[TxSequenceAddr, TxSequenceAddr, OR, cur_me, <<2]

init_common#:
.local jump_offset
	alu[jump_offset, --, B, cur_me, <<2]
	jump[jump_offset, port0#], targets[port0#, port1#, port2#, port3#]
.endlocal

port0#:
	alu[ring_num, --, B, RING_0, <<2]
	immed[base_element_for_port, ((EG_TBUF_ELEM_COUNT / NUMBER_OF_PORTS) * PORT_0)]
	br[me_specific_init_done#]
	nop

port1#:
	alu[ring_num, --, B, RING_1, <<2]
	immed[base_element_for_port, ((EG_TBUF_ELEM_COUNT / NUMBER_OF_PORTS) * PORT_1)]
	br[me_specific_init_done#]
	nop

port2#:
	alu[ring_num, --, B, RING_2, <<2]
	immed[base_element_for_port, ((EG_TBUF_ELEM_COUNT / NUMBER_OF_PORTS) * PORT_2)]
	br[me_specific_init_done#]
	nop

port3#:
	alu[ring_num, --, B, RING_3, <<2]
	immed[base_element_for_port, ((EG_TBUF_ELEM_COUNT / NUMBER_OF_PORTS) * PORT_3)]
	br[me_specific_init_done#]


me_specific_init_done#:
	immed[TBuf_Base, RBUF_TBUF]

	alu[sram_channel_number, --, B, CHAN_NUMBER, <<SRAM_CHANNEL_NUMBER_FIELD]
	alu[t0, sram_channel_number, OR, Q_NUMBER, <<SRAM_Q_ARRAY_NUMBER_FIELD]

	ctx_arb[voluntary]
	br!=ctx[0, wait_for_next_ctx_sig#]

init#:
	immed[@tbuf_element, 0]

	immed[@sramDescBase, (EG_SRAM_DESC_BASE & MASK_16BIT)]
	immed_w1[@sramDescBase, ((EG_SRAM_DESC_BASE >> 16) & MASK_16BIT)]

	immed[@dramPacketBase, (EG_DRAM_PCKT_BASE & MASK_16BIT)]
	immed_w1[@dramPacketBase, ((EG_DRAM_PCKT_BASE >> 16) & MASK_16BIT)]

	immed[@mask_qa, (BUFFER_ADDR_MASK & MASK_16BIT)]
	immed_w1[@mask_qa, ((BUFFER_ADDR_MASK >> 16) & MASK_16BIT)]		// Used to mask out the buffer address on dequeue

	.set_sig inter_me_sig
	ctx_arb[inter_me_sig]
	br[wake_up_next_thread_after_init#]


wait_for_next_ctx_sig#:
	.set_sig next_ctx_sig
	ctx_arb[next_ctx_sig]

wake_up_next_thread_after_init#:
	br=ctx[7, wait_for_assignment#]
	local_csr_wr[SAME_ME_SIGNAL, NEXT_CTX_SIG_DATA]

.begin
	.reg $scratch_data
// Get new assignment, i.e. the buf addr from scratch ring
wait_for_assignment#:
	scratch[get, $scratch_data, ring_num, 0, 1], ctx_swap[scratch_sig]
	alu[--, $scratch_data, -, 0]
	beq[wait_for_assignment#]		// branch to label if there is no new assignment
	alu[buf_addr, --, B, $scratch_data]
.end

.begin
	.reg $sram_data
	sram[read, $sram_data, buf_addr, sram_channel_number, 1], sig_done[sram_sig]
	alu[cur_tbuf_elem, base_element_for_port, +, @tbuf_element]
	alu[tbuf_count, --, B, @tbuf_element]
	alu[@tbuf_element, @tbuf_element, +, 1]
	alu[--, EG_TBUF_ELEM_COUNT_PER_PORT, -, @tbuf_element]
	bne[wait_for_sram_sig#]
	alu[@tbuf_element, --, B, 0]
/*	sram[read, $sram_data, buf_addr, sram_channel_number, 1], sig_done[sram_sig]
	alu[cur_tbuf_elem, base_element_for_port, +, @tbuf_element]
	alu[tbuf_count, --, B, @tx_count]
	alu[@tbuf_element, @tbuf_element, +, 1]
	alu[--, EG_TBUF_ELEM_COUNT_PER_PORT, -, @tbuf_element]
	bne[check_tx_count_wrap_around#]
	alu[@tbuf_element, --, B, 0]
check_tx_count_wrap_around#:
	alu[@tx_count, @tx_count, +, 1]
	alu[--, EG_TBUF_ELEM_COUNT, -, @tx_count]
	bne[wait_for_sram_sig#]
	alu[@tx_count, --, B, 0]
*/
/*	.reg $sram_data
	sram[read, $sram_data, buf_addr, sram_channel_number, 1], sig_done[sram_sig]
	alu[cur_tbuf_elem, base_element_for_port, +, @tbuf_element]
	alu[@tbuf_element, @tbuf_element, +, 1]
	alu[--, EG_TBUF_ELEM_COUNT_PER_PORT, -, @tbuf_element]
	bne[wait_for_sram_sig#]
	alu[@tbuf_element, --, B, 0]
*/

wait_for_sram_sig#:
	ctx_arb[sram_sig], defer[1]
	alu[buf_offset, buf_addr, -, @sramDescBase]
	alu[byte_count, --, B, $sram_data]
.end

/*
//*******************************************************
// Read the Transmit Sequence
//*******************************************************
.begin	
	.reg result tmp_val tmp_tbuf $TxSequenceData

read_tx_sequence_loop#:
	msf[read, $TxSequenceData, TxSequenceAddr, 0, 1], ctx_swap[msf_sig]

	alu[result, EG_TBUF_ELEM_COUNT_MASK, AND, $TxSequenceData]	// get mpkts actually sent
	alu[tmp_val, EG_TBUF_ELEM_COUNT_PER_PORT_MASK, AND, tbuf_count]
	alu[--, tmp_val, -, result]
	bge[cont_comp_tbuf_tx_sequnce#], defer[1]
	alu[tmp_tbuf, --, b, tmp_val]		
	alu[tmp_tbuf, tmp_tbuf, +, EG_TBUF_ELEM_COUNT]	// wrap around, add tbuf element number
cont_comp_tbuf_tx_sequnce#:
	alu[result, tmp_tbuf, -, result]			// compare with totals in tbuf
	alu[--, result, -, 8]						// compare with threshold
	bge[read_tx_sequence_loop#] 				// loop again
.end
*/
//*******************************************************
// Read the Transmit Sequence
//*******************************************************
.begin	
	.reg result tmp_val tmp_tbuf $TxSequenceData

read_tx_sequence_loop#:
	msf[read, $TxSequenceData, TxSequenceAddr, 0, 1], ctx_swap[msf_sig]

	alu[result, EG_TBUF_ELEM_COUNT_PER_PORT_MASK, AND, $TxSequenceData]	// get mpkts actually sent
	alu[tmp_val, EG_TBUF_ELEM_COUNT_PER_PORT_MASK, AND, tbuf_count]
	alu[--, tmp_val, -, result]
	bge[cont_comp_tbuf_tx_sequnce#], defer[1]
	alu[tmp_tbuf, --, b, tmp_val]		
	alu[tmp_tbuf, tmp_tbuf, +, EG_TBUF_ELEM_COUNT_PER_PORT]	// wrap around, add tbuf element number
cont_comp_tbuf_tx_sequnce#:
	alu[result, tmp_tbuf, -, result]			// compare with totals in tbuf
	alu[--, result, -, 8]						// compare with threshold
	bge[read_tx_sequence_loop#] 				// loop again
.end //result tmp_tbuf


//****************************************************
// Move data to TBUF from DRAM
//****************************************************
.begin
	.reg refcnt pkt_buf_addr cur_tbuf_addr

	alu[pkt_buf_addr, --, B, buf_offset, <<5]
	alu[pkt_buf_addr, pkt_buf_addr, +, @dramPacketBase]

	alu[cur_tbuf_addr, TBuf_Base, OR, cur_tbuf_elem, <<EG_TBUF_ADDR_SHF]
	alu[cur_tbuf_addr, --, B, cur_tbuf_addr, <<5]
	alu[cur_tbuf_addr, cur_tbuf_addr, OR, 1, <<4]		// set the overwrite bit for the TBUF addr

	alu[refcnt, --, B, byte_count, >>3]
	alu[--, byte_count, AND, 0x7]
	bne[refcnt_calc_done#]
	alu[refcnt, refcnt, -, 1]			// Calculate the refcnt for indirect ref
refcnt_calc_done#:
	alu[refcnt, --, B, refcnt, <<21]	// Shift to appropriate bit
	alu[refcnt, refcnt, OR, 1, <<25]	// Set the overwrite bit for refcnt

	alu[--, cur_tbuf_addr, OR, refcnt]	// indirect ref
	dram[tbuf_wr, --, pkt_buf_addr, 0, 8], indirect_ref, sig_done[dram_sig]
	ctx_arb[dram_sig]	
.end


//*******************************************************
// Write the Transmit Control Word with appropriate data
//*******************************************************
.begin 
	.reg MsfAddress temp

	immed[MsfAddress, TBUF_ELEMENT_CONTROL_V]
	alu[MsfAddress, MsfAddress, OR, cur_tbuf_elem, <<EG_TBUF_CTRL_ADDR_SHF]

	immed[temp, (TX_CONTROL_SOP | TX_CONTROL_EOP)]
	alu[$TxControlWord0, temp, OR, byte_count, <<24]		// For Tx Control Word

	immed[$TxControlWord1, 0]

	msf[write, $TxControlWord0, MsfAddress, 0, 2], ctx_swap[msf_sig]
.end


//*******************************************************
// Free buffer
//*******************************************************
.begin
	.reg cellcount enqueue_data

	alu[enqueue_data, --, B, buf_addr, >>2]
	immed[cellcount, 0x1c, <<16]		// set cell count to 1, set OV EOP, and SOP
	
	alu[--, cellcount, OR, 0]
	sram[enqueue,  --, t0, enqueue_data], indirect_ref
.end


br[wait_for_assignment#]