?? sys_loopback_pl_3_in_tx.uc
字號(hào):
/* line_rate_bw_in_tx.uc
*
*
*
* NOTE: THIS IS NOT A PERFORMANCE BENCHMARK!!!! IT IS JUST TO CHECK IF THE
* HARDWARE IS ABLE TO HANDLE DATA AT THE LINERATE THAT IS BEING
* PUMPED INTO THE SYSTEM
*
*---------------------------------------------------------------------------
*
* I N T E L P R O P R I E T A R Y
*
* COPYRIGHT (c) 2002 BY INTEL CORPORATION. ALL RIGHTS
* RESERVED. NO PART OF THIS PROGRAM OR PUBLICATION MAY
* BE REPRODUCED, TRANSMITTED, TRANSCRIBED, STORED IN A
* RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER
* LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,
* MAGNETIC, OPTICAL, CHEMICAL, MANUAL, OR OTHERWISE, WITHOUT
* THE PRIOR WRITTEN PERMISSION OF :
*
* INTEL CORPORATION
*
* 2200 MISSION COLLEGE BLVD
*
* SANTA CLARA, CALIFORNIA 95052-8119
*
*---------------------------------------------------------------------------
*
*
* system: IXDP2400
* subsystem: DIAG
* author: dalsraja, November 11, 2002
* revisions:
*
*
* --------------------------------------------------------------------------
*/
#include "sys_loopback_pl_3.h"
#define NEXT_CTX_SIGNAL IN_SAME_ME_SIG_NUM
#define BUFFER_ADDR_MASK 0xFFFFFF
#define SIG_CTX_DATA ((1 << 7) | (NEXT_CTX_SIGNAL << 3))
.reg sram_addr
.reg temp $temp
.reg MsfAddress MsfAddress0 MsfAddress1 TxSequenceAddr
.reg byte_count ring_num mask_qa
.reg TxConfigData0
.reg $TxConfigData0
.reg $TxControlWord0 $TxControlWord1
.reg $scratch_data0 $scratch_data1
.reg @tbuf_element cur_tbuf_elem
.reg buf_addr buf_offset rx_port_num pkt_buff_addr TBuf_Base cur_tbuf_addr
.reg sram_channel_number
.reg @sramDescBase @dramPacketBase t0
.reg $prepend_data0 $prepend_data1
.sig dram_sig sram_sig scratch_sig
.sig msf_sig next_ctx_sig
.xfer_order $TxControlWord0 $TxControlWord1
.xfer_order $scratch_data0 $scratch_data1
.xfer_order $prepend_data0 $prepend_data1
.addr next_ctx_sig IN_SAME_ME_SIG_NUM
init_common#:
immed[TxSequenceAddr, TX_SEQUENCE_0]
alu[ring_num, --, B, RING_0, <<2]
immed[TBuf_Base, RBUF_TBUF]
alu[sram_channel_number, --, B, CHAN_NUMBER, <<SRAM_CHANNEL_NUMBER_FIELD]
alu[t0, sram_channel_number, OR, Q_NUMBER, <<SRAM_Q_ARRAY_NUMBER_FIELD]
br!=ctx[0, wait_for_next_ctx_sig#]
init#:
immed[@tbuf_element, 0]
immed[@sramDescBase, (IN_SRAM_DESC_BASE & MASK_16BIT)]
immed_w1[@sramDescBase, ((IN_SRAM_DESC_BASE >> 16) & MASK_16BIT)]
immed[@dramPacketBase, (IN_DRAM_PCKT_BASE & MASK_16BIT)]
immed_w1[@dramPacketBase, ((IN_DRAM_PCKT_BASE >> 16) & MASK_16BIT)]
//****************************************************
// Configure Rx Control
//****************************************************
.begin
.reg RxControlData $RxControlData MsfAddress
immed[RxControlData, ((0<<9) | (IN_RX_ELEMENT_SIZE << 2))]
immed_w1[RxControlData, ((IN_RX_MODE << 6) | (IN_RX_WIDTH << 4) | (IN_RX_PHY << 3) | (0<<1)|(0<<0))]
alu[$RxControlData, --, B, RxControlData]
immed[MsfAddress, MSF_RX_CONTROL]
msf[write, $RxControlData, MsfAddress, 0, 1], ctx_swap[msf_sig]
.end
//******************************************************
// Initialize RBUF Freelist by freeing all the elements
//******************************************************
.begin
.reg temp_val temp_reg
immed[temp_val, 0]
init_RBUF#:
alu[temp_reg, --, B, temp_val, <<16]
msf[fast_wr, --, temp_reg, RBUF_ELEMENT_DONE]
alu[temp_val, temp_val, +, 1]
alu[--, IN_RBUF_ELEM_COUNT, -, temp_val]
bne[init_RBUF#]
.end
//******************************************************
// Configure Rx UP Control
//******************************************************
.begin
.reg RxUPControlData $RxUPControlData MsfAddress
immed[RxUPControlData, (UP_CTRL_PP_MODE_PLONE | UP_CTRL_CP_MODE | UP_CTRL_PARITY_ODD | UP_CTRL_CELLSIZE | UP_CTRL_DRTIME)]
// immed[RxUPControlData, (UP_CTRL_PP_MODE | UP_CTRL_CP_MODE | UP_CTRL_PARITY | UP_CTRL_CELLSIZE | UP_CTRL_DRTIME)]
alu[$RxUPControlData, --, B, RxUPControlData]
immed[MsfAddress, RX_UP_CONTROL_0]
msf[write, $RxUPControlData, MsfAddress, 0, 1], ctx_swap[msf_sig]
immed[MsfAddress, RX_UP_CONTROL_1]
msf[write, $RxUPControlData, MsfAddress, 0, 1], ctx_swap[msf_sig]
immed[MsfAddress, RX_UP_CONTROL_2]
msf[write, $RxUPControlData, MsfAddress, 0, 1], ctx_swap[msf_sig]
immed[MsfAddress, RX_UP_CONTROL_3]
msf[write, $RxUPControlData, MsfAddress, 0, 1], ctx_swap[msf_sig]
.end
//****************************************************
// Configure Rx Control
//****************************************************
.begin
.reg $RxControlData MsfAddress
immed[MsfAddress, MSF_RX_CONTROL]
msf[read, $RxControlData, MsfAddress, 0, 1], ctx_swap[msf_sig]
alu[$RxControlData, $RxControlData, OR, IN_RX_ENABLE_MASK, <<28]
msf[write, $RxControlData, MsfAddress, 0, 1], ctx_swap[msf_sig]
.end
//****************************************************
// Configure Tx Control
//****************************************************
.begin
.reg MsfAddress TxControlData $TxControlData
immed[MsfAddress, MSF_TX_CONTROL]
immed[TxControlData, (IN_TX_ELEMENTSIZE << 2)] // put control and data into diff freelist
immed_w1[TxControlData, ((IN_TX_ENABLE_MASK << 8) | (IN_TX_MODE << 6) | (IN_TX_WIDTH << 4) | (IN_TX_PHY << 3) | (0<<1)|(1<<0))]
alu[$TxControlData, --, B, TxControlData]
msf[write, $TxControlData, MsfAddress, 0, 1], ctx_swap[msf_sig]
alu[$TxControlData, TxControlData, OR, IN_TX_ENABLE_MASK, <<28]
msf[write, $TxControlData, MsfAddress, 0, 1], ctx_swap[msf_sig]
.end
//****************************************************
// Configure Rx Thread Freelist Timeout
//****************************************************
.begin
.reg timeout_val
immed[timeout_val, FREELIST_TIMEOUT_VAL]
alu[timeout_val,--, B, timeout_val, <<16] // timeout value
msf[fast_wr, --, timeout_val, RX_THREAD_FREELIST_TIMEOUT_0]
msf[fast_wr, --, timeout_val, RX_THREAD_FREELIST_TIMEOUT_1]
msf[fast_wr, --, timeout_val, RX_THREAD_FREELIST_TIMEOUT_2]
msf[fast_wr, --, timeout_val, RX_THREAD_FREELIST_TIMEOUT_3]
.end
//****************************************************
// Set up the freelist (queue)
//****************************************************
.begin
.reg cellcount freelist sr0
.reg $s0 $s1 $s2
.reg tmp
.sig qa_init addr
.reg $sr0 $sr1 $sr2 $sr3
.reg sram_desc_base
.xfer_order $sr0 $sr1 $sr2 $sr3
.xfer_order $s0 $s1 $s2
immed[sram_desc_base, (IN_SRAM_DESC_BASE & MASK_16BIT)]
immed_w1[sram_desc_base, ((IN_SRAM_DESC_BASE >> 16) & MASK_16BIT)]
alu[tmp, --, B, CHAN_NUMBER, <<SRAM_CHANNEL_NUMBER_FIELD]
alu[tmp, tmp, OR, sram_desc_base]
immed[$s0, 0]
immed[$s1, 0]
immed[$s2, 0]
sram[write, $s0, tmp, 0, 3], ctx_swap[qa_init]
alu[tmp, --, B, sram_desc_base]
alu[tmp, --, B, tmp, >>2]
sram[rd_qdesc_head, $sr0, t0, tmp, 2], ctx_swap[qa_init]
sram[rd_qdesc_other, --, t0, tmp]
immed[freelist, (FREELIST_SIZE & MASK_16BIT)]
immed_w1[freelist, ((FREELIST_SIZE >> 16) & MASK_16BIT)]
immed[cellcount, 0x1c, <<16] //set cell count to 1, set OV EOP, and SOP
addfreelist#:
alu[--, cellcount, OR, 0]
sram[enqueue, --, t0, tmp], indirect_ref
alu[tmp, tmp, +, 1]
alu[freelist, freelist, -, 1]
bne[addfreelist#]
.end
//**************************************************
// Configure Scratch Ring
//**************************************************
.begin
.reg $scratch_base $scratch_head $scratch_tail
.sig scratch_sig1 scratch_sig2 scratch_sig3
alu[$scratch_base, --, B, 0x3, <<30] // Use ring size of 1024 lw and base 0x0
immed[$scratch_head,0]
immed[$scratch_tail,0]
cap[write, $scratch_base, SCRATCH_RING_BASE_0],sig_done[scratch_sig1]
cap[write, $scratch_head, SCRATCH_RING_HEAD_0],sig_done[scratch_sig2]
cap[write, $scratch_tail, SCRATCH_RING_TAIL_0],sig_done[scratch_sig3]
ctx_arb[scratch_sig1, scratch_sig2, scratch_sig3]
.end
//**************************************************
// Signal Receive MEs
//**************************************************
immed[temp, ((IN_ME_RX_0 << 7) | (IN_SIG_THD_NUM << 4) | (IN_INTER_ME_SIG_NUM << 0))]
alu[--, --, B, temp]
cap[fast_wr, ALU, interthread_sig] // to signal Rx ME that Tx has finished its init
immed[temp, ((IN_ME_RX_1 << 7) | (IN_SIG_THD_NUM << 4) | (IN_INTER_ME_SIG_NUM << 0))]
alu[--, --, B, temp]
cap[fast_wr, ALU, interthread_sig] // to signal Rx ME that Tx has finished its init
immed[temp, ((IN_ME_RX_2 << 7) | (IN_SIG_THD_NUM << 4) | (IN_INTER_ME_SIG_NUM << 0))]
alu[--, --, B, temp]
cap[fast_wr, ALU, interthread_sig] // to signal Rx ME that Tx has finished its init
immed[temp, ((IN_ME_RX_3 << 7) | (IN_SIG_THD_NUM << 4) | (IN_INTER_ME_SIG_NUM << 0))]
alu[--, --, B, temp]
cap[fast_wr, ALU, interthread_sig] // to signal Rx ME that Tx has finished its init
br[wake_up_next_thread_after_init#]
wait_for_next_ctx_sig#:
.set_sig next_ctx_sig
ctx_arb[next_ctx_sig]
wake_up_next_thread_after_init#:
br=ctx[7, wait_for_assignment#]
local_csr_wr[SAME_ME_SIGNAL, SIG_CTX_DATA]
wait_for_assignment#:
.local $scratch_data
// Get new assignment, i.e. the buf addr from scratch ring
scratch[get, $scratch_data, ring_num, 0, 1], ctx_swap[scratch_sig]
alu[--, $scratch_data, -, 0]
beq[wait_for_assignment#] // branch to label if there is no new assignment
alu[buf_addr, --, B, $scratch_data]
.endlocal
.local $sram_data
sram[read, $sram_data, buf_addr, sram_channel_number, 1], sig_done[sram_sig]
alu[cur_tbuf_elem, --, B, @tbuf_element]
alu[@tbuf_element, @tbuf_element, +, 1]
alu[--, IN_TBUF_ELEM_COUNT, -, @tbuf_element]
bne[wait_for_sram_sig#]
alu[@tbuf_element, --, B, 0]
wait_for_sram_sig#:
ctx_arb[sram_sig], defer[1]
alu[buf_offset, buf_addr, -, @sramDescBase]
alu[byte_count, --, B, $sram_data, >>4]
alu[$prepend_data0, MASK_4BIT, AND, $sram_data] // Port number
alu[$prepend_data1, --, B, byte_count]
.endlocal
/*
//*******************************************************
// Read the Transmit Sequence
//*******************************************************
.begin
.reg result tmp_val tmp_tbuf $TxSequenceData
read_tx_sequence_loop#:
msf[read, $TxSequenceData, TxSequenceAddr, 0, 1], ctx_swap[msf_sig]
alu[result, TBUF_ELEM_COUNT_4PORT_MASK, AND, $TxSequenceData] // get mpkts actually sent
alu[tmp_val, TBUF_ELEM_COUNT_4PORT_MASK, AND, cur_tbuf_elem]
alu[--, tmp_val, -, result]
bge[cont_comp_tbuf_tx_sequnce#], defer[1]
alu[tmp_tbuf, --, b, tmp_val]
alu[tmp_tbuf, tmp_tbuf, +, TBUF_ELEM_COUNT_4PORT] // wrap around, add tbuf element number
cont_comp_tbuf_tx_sequnce#:
alu[result, tmp_tbuf, -, result] // compare with totals in tbuf
alu[--, result, -, 8] // compare with threshold
bge[read_tx_sequence_loop#] // loop again
.end //result tmp_tbuf
*/
//****************************************************
// Move data to TBUF from DRAM
//****************************************************
.begin
.reg refcnt pkt_buf_addr
.reg prepend_tbuf_addr
alu[cur_tbuf_addr, TBuf_Base, OR, cur_tbuf_elem, <<IN_TBUF_ADDR_SHF]
// alu[prepend_tbuf_addr, --, B, cur_tbuf_addr]
msf[write64, $prepend_data0, cur_tbuf_addr, 0, 1], sig_done[msf_sig]
alu[pkt_buf_addr, --, B, buf_offset, <<5]
alu[pkt_buf_addr, pkt_buf_addr, +, @dramPacketBase]
alu[cur_tbuf_addr, cur_tbuf_addr, +, PREPEND_LENGTH]
alu[cur_tbuf_addr, --, B, cur_tbuf_addr, <<5]
alu[cur_tbuf_addr, cur_tbuf_addr, OR, 1, <<4] // set the overwrite bit for the TBUF addr
alu[refcnt, --, B, byte_count, >>3]
alu[--, byte_count, AND, 0x7]
bne[refcnt_calc_done#]
alu[refcnt, refcnt, -, 1] // Calculate the refcnt for indirect ref
refcnt_calc_done#:
alu[refcnt, --, B, refcnt, <<21] // Shift to appropriate bit
alu[refcnt, refcnt, OR, 1, <<25] // Set the overwrite bit for refcnt
alu[--, cur_tbuf_addr, OR, refcnt] // indirect ref
dram[tbuf_wr, --, pkt_buf_addr, 0, 8], indirect_ref, sig_done[dram_sig]
ctx_arb[msf_sig, dram_sig]
.end
//*******************************************************
// Write the Transmit Control Word with appropriate data
//*******************************************************
.begin
.reg MsfAddress
immed[MsfAddress, TBUF_ELEMENT_CONTROL_V]
alu[MsfAddress, MsfAddress, OR, cur_tbuf_elem, <<3]
immed[temp, CSIX_UNICAST]
alu[temp, temp, OR, PREPEND_LENGTH, <<16] // prepend length
alu[$TxControlWord0, temp, OR, byte_count, <<24] // For Tx Control Word
immed[temp, (EXT_HDR & MASK_16BIT)]
immed_w1[temp, ((EXT_HDR >> 16) & MASK_16BIT)]
alu[$TxControlWord1, --, B, temp] // Setting extension header
msf[write, $TxControlWord0, MsfAddress, 0, 2], ctx_swap[msf_sig]
.end
//*******************************************************
// Free buffer
//*******************************************************
.begin
.reg temp cellcount
alu[temp, --, B, buf_addr, >>2]
immed[cellcount, 0x1c, <<16] // set OV EOP, and SOP
alu[--, cellcount, OR, 0]
sram[enqueue, --, t0, temp], indirect_ref
.end
br[wait_for_assignment#]
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