/* emi_bw_tx.uc
 *
 * Brief:
 *
 *
 *---------------------------------------------------------------------------
 *                                                                      
 *                  I N T E L   P R O P R I E T A R Y                   
 *                                                                      
 *     COPYRIGHT (c)  2002 BY  INTEL  CORPORATION.  ALL RIGHTS          
 *     RESERVED.   NO  PART  OF THIS PROGRAM  OR  PUBLICATION  MAY      
 *     BE  REPRODUCED,   TRANSMITTED,   TRANSCRIBED,   STORED  IN  A    
 *     RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER    
 *     LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,    
 *     MAGNETIC,  OPTICAL,  CHEMICAL, MANUAL, OR OTHERWISE,  WITHOUT    
 *     THE PRIOR WRITTEN PERMISSION OF :                                
 *                                                                      
 *                        INTEL  CORPORATION                            
 *                                                                     
 *                     2200 MISSION COLLEGE BLVD                        
 *                                                                      
 *               SANTA  CLARA,  CALIFORNIA  95052-8119                  
 *                                                                      
 *---------------------------------------------------------------------------
 *
 *
 *  system: IXDP2400
 *  subsystem: DIAG
 *  author: dalsraja, 23 December, 2002
 *  revisions: 
 * 
 * 
 * --------------------------------------------------------------------------
 */


#include "common_uc.h"
#include "sys_loopback_bd_3.h"

#define TX_ELEMENT_SIZE				MSF_ELEMENTSIZE_128
#define TX_ENABLE_MASK				0x1
#define TX_MODE						MSF_POS_UTOPIA
#define TX_WIDTH					MSF_WIDTH_1x32
#define TX_SINGLE_PHY				MSF_SINGLE_PHY

#define TBUF_ELEM_COUNT				(1 << (7 - TX_ELEMENT_SIZE))
#define TBUF_ADDR_SHF				(6 + TX_ELEMENT_SIZE)
#define TX_ELEMENTSIZE_BYTE			(1 << TBUF_ADDR_SHF)

#define POS_PAYLOAD_LENGTH			48
#define FUTURE_COUNT_SIG_NUM		&future_count_sig
#define FUTURE_COUNT_STEP			35

#define FUTURE_COUNT_STEP_ADDR		0x1600
#define LOOP_COUNT_ADDR				0x1604
#define BURST_COUNT_ADDR			0x1608
#define XSCALE_MSG_ADDR				0x1610

#define INTER_ME_SIG_NUM			15

#define SIG_THD_NUM					0

.reg MsfAddress TxSequenceAddr
.reg pkt_in_one_burst pkt_in_cur_burst
.reg total_loop cur_loop
.reg future_count_value future_count_incr
.reg byte_count
.reg $misc_ctrl_val
.reg TxConfigData0
.reg $TxConfigData0
.reg $TxControlWord0 $TxControlWord1
.reg tbuf_element base_element_for_port
.sig msf_sig future_count_sig inter_me_sig cap_sig

.xfer_order $TxControlWord0 $TxControlWord1

.addr inter_me_sig INTER_ME_SIG_NUM

.set_sig inter_me_sig
br=ctx[0, init#]
ctx_arb[kill]

init#:
//	immed[total_packets_tx, 0]
	immed[tbuf_element, 0]
	immed[byte_count, POS_PAYLOAD_LENGTH]
	immed[cur_loop, 0]
	immed[future_count_incr, FUTURE_COUNT_STEP]
	immed[TxSequenceAddr, TX_SEQUENCE_0]

.begin
	.reg temp_scratch_addr $temp_scratch_data
	.sig scratch_sig
	immed[temp_scratch_addr, FUTURE_COUNT_STEP_ADDR]
	scratch[read, $temp_scratch_data, temp_scratch_addr, 0, 1], ctx_swap[scratch_sig]
	alu[future_count_incr, --, B, $temp_scratch_data]
.end

.begin
	.reg temp_scratch_addr $temp_scratch_data
	.sig scratch_sig
	immed[temp_scratch_addr, LOOP_COUNT_ADDR]
	scratch[read, $temp_scratch_data, temp_scratch_addr, 0, 1], ctx_swap[scratch_sig]
	alu[total_loop, --, B, $temp_scratch_data]
.end

.begin
	.reg temp_scratch_addr $temp_scratch_data
	.sig scratch_sig
	immed[temp_scratch_addr, BURST_COUNT_ADDR]
	scratch[read, $temp_scratch_data, temp_scratch_addr, 0, 1], ctx_swap[scratch_sig]
	alu[pkt_in_one_burst, --, B, $temp_scratch_data]
.end

init_msf#:
//****************************************************
// Configure TX Control
//****************************************************
	immed[MsfAddress, MSF_TX_CONTROL]
	immed[TxConfigData0, (TX_ELEMENT_SIZE << 2)]	// put control and data into diff freelist
	immed_w1[TxConfigData0, ((TX_ENABLE_MASK << 8) | (TX_MODE << 6) | (TX_WIDTH << 4) | (TX_SINGLE_PHY << 3) | (0<<1)|(0<<0))]
	alu[$TxConfigData0, --, B, TxConfigData0]
	msf[write, $TxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]


//******************************************************
// Configure TX UP Control CSRs 
//******************************************************
	immed[MsfAddress, TX_UP_CONTROL_0]
	immed[TxConfigData0, (UP_CTRL_CP_MODE | UP_CTRL_PARITY | UP_CTRL_CELLSIZE | UP_CTRL_DRTIME)]
	alu[$TxConfigData0, --, B, TxConfigData0]
	msf[write, $TxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]


//****************************************************
// Configure TX Control
//****************************************************
	immed[MsfAddress, MSF_TX_CONTROL]
	immed[TxConfigData0, (TX_ELEMENT_SIZE << 2)]	// put control and data into diff freelist
	immed_w1[TxConfigData0, ((TX_ENABLE_MASK << 12) | (TX_ENABLE_MASK << 8) | (TX_MODE << 6) | (TX_WIDTH << 4) | (TX_SINGLE_PHY << 3) | (0<<1)|(0<<0))]
	alu[$TxConfigData0, --, B, TxConfigData0]
	msf[write, $TxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]


msf_init_done#:
	cap[read, $misc_ctrl_val, MISC_CONTROL], ctx_swap[cap_sig]	// Read the MISC_CONTROL reg
	
next_burst#:
//****************************************************
// Configure the TIMESTAMP registers and configure
// the FUTURE_COUNT_SIGNAL register
//****************************************************
	immed[pkt_in_cur_burst, 0]
	immed[future_count_value, 0]
	local_csr_wr[TIMESTAMP_LOW, 0]
	local_csr_wr[TIMESTAMP_HIGH, 0]
	local_csr_wr[CSR_CTX_POINTER, 0]
	local_csr_wr[INDIRECT_FUTURE_COUNT_SIGNAL, FUTURE_COUNT_SIG_NUM]

	alu[--, $misc_ctrl_val, OR, 1, <<7]		// Set the timestamp enable bit
	cap[fast_wr, alu, MISC_CONTROL]			// and write to the MISC_CONTROL register

next_packet#:
	local_csr_wr[CSR_CTX_POINTER, 0]
	alu[future_count_value, future_count_value, +, future_count_incr]
	alu[future_count_value, 0, +16, future_count_value]
	local_csr_wr[INDIRECT_CTX_FUTURE_COUNT, future_count_value]

.set_sig future_count_sig
//*******************************************************
// Write the Transmit Control Word with appropriate data
//*******************************************************
.begin
	.reg temp

	immed[MsfAddress, TBUF_ELEMENT_CONTROL_V]
	alu[MsfAddress, MsfAddress, OR, tbuf_element, <<3]

	immed[temp, (TX_CONTROL_SOP | TX_CONTROL_EOP)]
	alu[$TxControlWord0, temp, OR, byte_count, <<24]

	immed[$TxControlWord1, 0]

	ctx_arb[future_count_sig]

	msf[write, $TxControlWord0, MsfAddress, 0, 2], sig_done[msf_sig]
.end

	alu[tbuf_element, tbuf_element, +, 1]
	alu[tbuf_element, tbuf_element, AND, (TBUF_ELEM_COUNT - 1)]
	alu[pkt_in_cur_burst, pkt_in_cur_burst, +, 1]

.begin
	.reg $temp_reg_val temp_mask
	.reg temp_scratch_addr $temp_scratch_data
	.sig scratch_sig

	.if (pkt_in_cur_burst == pkt_in_one_burst)
		alu[$temp_reg_val, --, B, $misc_ctrl_val]			// Set the timestamp disable bit
		cap[write, $temp_reg_val, MISC_CONTROL], sig_done[cap_sig]	// and write to the MISC_CONTROL register

		.if (total_loop > 0)
			alu[cur_loop, cur_loop, +, 1]

//			.if (cur_loop == total_loop)
//				ctx_arb[kill]
//			.endif
		.endif

		ctx_arb[msf_sig, cap_sig]

		immed[temp_scratch_addr, XSCALE_MSG_ADDR]
		immed[$temp_scratch_data, 0xFFFF]
wait_for_xscale#:
		scratch[test_and_clr, $temp_scratch_data, temp_scratch_addr, 0], sig_done[scratch_sig]
		ctx_arb[scratch_sig]
		alu[--, --, B, $temp_scratch_data]
		beq[wait_for_xscale#]

		br[next_burst#]
	.else
		ctx_arb[msf_sig]
	.endif
.end

	br[next_packet#]