?? sys_loopback_bw_3_eg_rx.uc
字號:
/* line_rate_bw_eg_rx.uc
*
*
*
* NOTE: THIS IS NOT A PERFORMANCE BENCHMARK!!!! IT IS JUST TO CHECK IF THE
* HARDWARE IS ABLE TO HANDLE DATA AT THE LINERATE THAT IS BEING
* PUMPED INTO THE SYSTEM
*
*---------------------------------------------------------------------------
*
* I N T E L P R O P R I E T A R Y
*
* COPYRIGHT (c) 2002 BY INTEL CORPORATION. ALL RIGHTS
* RESERVED. NO PART OF THIS PROGRAM OR PUBLICATION MAY
* BE REPRODUCED, TRANSMITTED, TRANSCRIBED, STORED IN A
* RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER
* LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,
* MAGNETIC, OPTICAL, CHEMICAL, MANUAL, OR OTHERWISE, WITHOUT
* THE PRIOR WRITTEN PERMISSION OF :
*
* INTEL CORPORATION
*
* 2200 MISSION COLLEGE BLVD
*
* SANTA CLARA, CALIFORNIA 95052-8119
*
*---------------------------------------------------------------------------
*
*
* system: IXDP2400
* subsystem: DIAG
* author: dalsraja, November 11, 2002
* revisions:
*
*
* --------------------------------------------------------------------------
*/
#include "common_uc.h"
#include "sys_loopback_bw_3.h"
#define RX_TRANSFER_THREAD &$TransferReg00
#define RX_SIGNAL &rx_sig
#define NEXT_CTX_SIGNAL_NUM EG_SAME_ME_SIG_NUM
#define NEXT_CTX_SIG_DATA ((1 << 7) | (NEXT_CTX_SIGNAL_NUM << 3))
#define LOOP_COUNT_ADDR 0x1604
#define BURST_COUNT_ADDR 0x1608
#define ME_TO_XSCALE_MSG_ADDR 0x160C
#define XSCALE_MSG_ADDR 0x1610
#define SCRATCH_MSG_ADDR 0x1000
.reg cur_me cur_ctx
.reg sram_channel_number t0 $sr0
.reg @total_rx @total_packet
.reg @cur_loop @total_loop
.reg ring
.reg RxConfigData
.reg RBuf_Base Rbuf_Elem_Done Rx_Thd_Freelist
.reg null error elem bytecnt
.reg $prepend_data0 $prepend_data1 $data_4byte
.reg $ring_data
.reg @sramDescBase @dramPacketBase
.reg @expected_sequence_0 @expected_sequence_1 @expected_sequence_2 @expected_sequence_3
.reg $TransferReg00 $TransferReg01
.sig rx_sig
.sig next_ctx_sig
.sig msf_sig scratch_sig sram_sig dram_sig ring_sig
.xfer_order $TransferReg00 $TransferReg01
.xfer_order $prepend_data0 $prepend_data1 $data_4byte
.addr next_ctx_sig EG_SAME_ME_SIG_NUM
.set $TransferReg00
.begin
.reg temp_data
local_csr_rd[ACTIVE_CTX_STS]
immed[temp_data, 0]
alu[cur_me, 0x1F, AND, temp_data, >>3] // Extract the current ME number
alu[cur_ctx, 0x7, AND, temp_data] // Extract the current context number
.end
immed[ring, (RING_0 << 2)] // ring number in a register
alu[sram_channel_number, --, B, CHAN_NUMBER, <<SRAM_CHANNEL_NUMBER_FIELD]
alu[t0, sram_channel_number, OR, Q_NUMBER, <<SRAM_Q_ARRAY_NUMBER_FIELD]
immed[RBuf_Base, RBUF_TBUF ]
immed[Rbuf_Elem_Done, RBUF_ELEMENT_DONE]
immed[Rx_Thd_Freelist, RX_THREAD_FREELIST_0]
.begin
.reg RxThreadList temp_data me_data
alu[me_data, 0x3, AND, cur_me]
alu[temp_data, --, B, cur_me, >>4]
alu[me_data, me_data, OR, temp_data, <<2]
immed[RxThreadList, (RX_SIGNAL << 12)]
alu[RxThreadList, RxThreadList, OR, me_data, <<7]
alu[RxThreadList, RxThreadList, OR, cur_ctx, <<4]
alu[RxConfigData, RxThreadList, OR , RX_TRANSFER_THREAD]
alu[RxConfigData, --, B, RxConfigData, <<16] // Shift 16 for msf[fast_wr...]
.end
br=ctx[0, init_thread0_only#]
.set_sig next_ctx_sig
ctx_arb[next_ctx_sig]
br[ReceiveNextPacket#]
init_thread0_only#:
immed[@sramDescBase, (EG_SRAM_DESC_BASE & MASK_16BIT)]
immed_w1[@sramDescBase, ((EG_SRAM_DESC_BASE >> 16) & MASK_16BIT)]
immed[@dramPacketBase, (EG_DRAM_PCKT_BASE & MASK_16BIT)]
immed_w1[@dramPacketBase, ((EG_DRAM_PCKT_BASE >> 16) & MASK_16BIT)]
immed[@expected_sequence_0, 0]
immed[@expected_sequence_1, 0]
immed[@expected_sequence_2, 0]
immed[@expected_sequence_3, 0]
immed[@total_rx, 0]
immed[@cur_loop, 0]
.begin
.reg temp_scratch_addr $temp_scratch_data temp_data
.sig scratch_sig
immed[temp_scratch_addr, BURST_COUNT_ADDR]
scratch[read, $temp_scratch_data, temp_scratch_addr, 0, 1], ctx_swap[scratch_sig]
alu[temp_data, --, B, $temp_scratch_data, <<2] //multiply by 4 as there are 4 ports
alu[@total_packet, --, B, temp_data]
.end
.begin
.reg temp_scratch_addr $temp_scratch_data
.sig scratch_sig
immed[temp_scratch_addr, LOOP_COUNT_ADDR]
scratch[read, $temp_scratch_data, temp_scratch_addr, 0, 1], ctx_swap[scratch_sig]
alu[@total_loop, --, B, $temp_scratch_data]
.end
//****************************************************
// Configure RX/TX Control
//****************************************************
.begin
.reg MsfAddress RxControlData $RxControlData
immed[RxControlData, ((0<<9) | (EG_RX_ELEMENT_SIZE << 2))] // put control and data into diff freelist
immed_w1[RxControlData, ((EG_RX_MODE << 6) | (EG_RX_WIDTH << 4) | (EG_RX_PHY << 3) | (0 << 1) | (1 << 0))]
alu[$RxControlData, --, B, RxControlData]
immed[MsfAddress, MSF_RX_CONTROL]
msf[write, $RxControlData, MsfAddress, 0, 1], ctx_swap[msf_sig]
.end
//****************************************************
// Configure CSIX_TYPE_MAP
//****************************************************
.begin
.reg MsfAddress $CsixTypeMapData
alu[$CsixTypeMapData, --, B, MSF_CSIX_RBUF_DATA, <<BIT_SHF_UNICAST]
immed[MsfAddress, CSIX_TYPE_MAP]
msf[write, $CsixTypeMapData, MsfAddress, 0, 1], ctx_swap[msf_sig]
.end
//******************************************************
// Initialize RBUF Freelist to add elements to the list
//******************************************************
.begin
.reg temp_reg RbufElemDoneData
immed[temp_reg, 0]
init_RBUF#:
alu[RbufElemDoneData, --, B, temp_reg, <<16]
msf[fast_wr, --, RbufElemDoneData, RBUF_ELEMENT_DONE]
alu[temp_reg, temp_reg, +, 1]
alu[--, EG_RBUF_ELEM_COUNT, -, temp_reg]
bne[init_RBUF#]
.end
//****************************************************
// Configure RX/TX Control
//****************************************************
.begin
.reg MsfAddress RxControlData $RxControlData
immed[MsfAddress, MSF_RX_CONTROL]
msf[read, $RxControlData, MsfAddress, 0, 1], ctx_swap[msf_sig]
alu[$RxControlData, $RxControlData, OR, EG_RX_ENABLE_MASK, <<28]
msf[write, $RxControlData, MsfAddress, 0, 1], ctx_swap[msf_sig]
.end
//******************************************************
// Configure Rx_Thread_Freelist_Timeout0
//******************************************************
.begin
.reg timeout_val
immed[timeout_val, FREELIST_TIMEOUT_VAL] // timeout value
alu[timeout_val,--, B, timeout_val, <<16] // Shift 16 for fast_wr
msf[fast_wr, --, timeout_val, RX_THREAD_FREELIST_TIMEOUT_0]
.end
//****************************************************
// Configure TX Control
//****************************************************
.begin
.reg MsfAddress TxControlData $TxControlData
immed[MsfAddress, MSF_TX_CONTROL]
immed[TxControlData, (EG_TX_ELEMENTSIZE << 2)] // put control and data into diff freelist
immed_w1[TxControlData, ((EG_TX_ENABLE_MASK << 8) | (EG_TX_MODE << 6) | (EG_TX_WIDTH << 4) | (EG_TX_PHY << 3) | (0<<1)|(1<<0))]
alu[$TxControlData, --, B, TxControlData]
msf[write, $TxControlData, MsfAddress, 0, 1], ctx_swap[msf_sig]
.end
//******************************************************
// Configure Tx UP Control
//******************************************************
.begin
.reg MsfAddress TxUPControlData $TxUPControlData
immed[TxUPControlData, (UP_CTRL_CP_MODE | UP_CTRL_PARITY | UP_CTRL_CELLSIZE | UP_CTRL_DRTIME)]
alu[$TxUPControlData, --, B, TxUPControlData]
immed[MsfAddress, TX_UP_CONTROL_0]
msf[write, $TxUPControlData, MsfAddress, 0, 1], ctx_swap[msf_sig]
immed[MsfAddress, TX_UP_CONTROL_1]
msf[write, $TxUPControlData, MsfAddress, 0, 1], ctx_swap[msf_sig]
immed[MsfAddress, TX_UP_CONTROL_2]
msf[write, $TxUPControlData, MsfAddress, 0, 1], ctx_swap[msf_sig]
immed[MsfAddress, TX_UP_CONTROL_3]
msf[write, $TxUPControlData, MsfAddress, 0, 1], ctx_swap[msf_sig]
.end
//****************************************************
// Configure TX Control
//****************************************************
.begin
.reg MsfAddress TxControlData $TxControlData
immed[MsfAddress, MSF_TX_CONTROL]
msf[read, $TxControlData, MsfAddress, 0, 1], ctx_swap[msf_sig]
alu[$TxControlData, $TxControlData, OR, EG_TX_ENABLE_MASK, <<28]
msf[write, $TxControlData, MsfAddress, 0, 1], ctx_swap[msf_sig]
.end
//**************************************************
// Configure Scratch Ring
//**************************************************
.begin
.reg $scratch_base $scratch_head $scratch_tail temp_val
.sig scratch_sig1 scratch_sig2 scratch_sig3
alu[temp_val, --, B, RINGBASE_256_0, <<9]
alu[$scratch_base, temp_val, OR, RINGSIZE_1024, <<30] // Use ring size of 256 lw and base 0x0
immed[$scratch_head,0]
immed[$scratch_tail,0]
cap[write,$scratch_base,SCRATCH_RING_BASE_0],sig_done[scratch_sig1]
cap[write,$scratch_head,SCRATCH_RING_HEAD_0],sig_done[scratch_sig2]
cap[write,$scratch_tail,SCRATCH_RING_TAIL_0],sig_done[scratch_sig3]
ctx_arb[scratch_sig1, scratch_sig2, scratch_sig3]
.end
ReceiveNextPacket#:
local_csr_wr[SAME_ME_SIGNAL, NEXT_CTX_SIG_DATA]
msf[fast_wr, --, Rx_Thd_Freelist, RxConfigData] // add thread to freelist
.set_sig rx_sig next_ctx_sig
ctx_arb[rx_sig, next_ctx_sig]
// RSW should be in xfer register
// Transfer RBUF data to sram_in transfer registers
//***************************************
// Extract RSW
//***************************************
RSW#:
alu[null, 0x1, AND, $TransferReg00, >>9] // Extract null
bne[NULL#] // If null=1, result=0
// alu[error, 0x1, AND, $TransferReg00, >>13]
alu[elem, 0xFF, AND, $TransferReg00, >>24] // RBUF element number
.begin
.reg refcnt ind_ref_data
local_csr_wr[SAME_ME_SIGNAL, NEXT_CTX_SIG_DATA]
.local RBufAddress
alu[RBufAddress, RBuf_Base, OR, elem, <<EG_RBUF_ADDR_SHF]
msf[read, $prepend_data0, RBufAddress, 0, 3], sig_done[msf_sig] // Extract prepend data and first 4 bytes
alu[ind_ref_data, RBufAddress, +, PREPEND_LENGTH] // Calc. RBuf address for packet data
.endlocal // RBufAddress
.set_sig next_ctx_sig
ctx_arb[msf_sig, next_ctx_sig], defer[2]
alu[bytecnt, 0xFF, AND, $TransferReg00, >>16] // Extract byte count
alu[bytecnt, bytecnt, -, PREPEND_LENGTH] // Subtract prepend data length
.end
.if (bytecnt != $prepend_data1)
br[size_error#]
.endif
.begin
.reg temp_sequence
alu[temp_sequence, --, B, $data_4byte, >>24]
.if ($prepend_data0 == 0)
.if (temp_sequence == @expected_sequence_0)
alu[@expected_sequence_0, @expected_sequence_0, +, 1]
alu[@expected_sequence_0, @expected_sequence_0, AND, (EG_TBUF_ELEM_COUNT_PER_PORT - 1)]
.else
br[sequence_error#]
.endif
.elif ($prepend_data0 == 1)
.if (temp_sequence == @expected_sequence_1)
alu[@expected_sequence_1, @expected_sequence_1, +, 1]
alu[@expected_sequence_1, @expected_sequence_1, AND, (EG_TBUF_ELEM_COUNT_PER_PORT - 1)]
.else
br[sequence_error#]
.endif
.elif ($prepend_data0 == 2)
.if (temp_sequence == @expected_sequence_2)
alu[@expected_sequence_2, @expected_sequence_2, +, 1]
alu[@expected_sequence_2, @expected_sequence_2, AND, (EG_TBUF_ELEM_COUNT_PER_PORT - 1)]
.else
br[sequence_error#]
.endif
.elif ($prepend_data0 == 3)
.if (temp_sequence == @expected_sequence_3)
alu[@expected_sequence_3, @expected_sequence_3, +, 1]
alu[@expected_sequence_3, @expected_sequence_3, AND, (EG_TBUF_ELEM_COUNT_PER_PORT - 1)]
.else
br[sequence_error#]
.endif
.else
br[rec_error#]
.endif
.end
//**************************************************************
// Free up Element by writing to RBUF_Element_Done
//**************************************************************
.begin
.reg rbuf_elem_done_data
alu[rbuf_elem_done_data, --, B, elem, <<16]
msf[fast_wr, --, rbuf_elem_done_data, RBUF_ELEMENT_DONE]
.end
alu[@total_rx, @total_rx, +, 1]
.if (@total_rx == @total_packet)
immed[@total_rx, 0]
// .if (@total_loop > 0)
alu[@cur_loop, @cur_loop, +, 1]
/* .if (@cur_loop == @total_loop)
.begin
.reg $temp_scratch temp_scratch_addr
immed[$temp_scratch, TEST_COMPLETE]
immed[temp_scratch_addr, SCRATCH_MSG_ADDR]
scratch[write, $temp_scratch, temp_scratch_addr, 0, 1], ctx_swap[scratch_sig]
.end
.endif
*/// .endif
alu[$ring_data, --, B, @cur_loop]
check_ring_full#:
br_inp_state[SCR_Ring0_Full, check_ring_full#]
scratch[put, $ring_data, ring, 0, 1], ctx_swap[ring_sig]
/* .begin
.reg $temp_scratch0 $temp_scratch1 $temp_scratch2 $temp_scratch3 temp_scratch_addr
.xfer_order $temp_scratch0 $temp_scratch1 $temp_scratch2 $temp_scratch3
immed[$temp_scratch0, 1]
immed[$temp_scratch1, 1]
immed[$temp_scratch2, 1]
immed[$temp_scratch3, 1]
immed[temp_scratch_addr, XSCALE_MSG_ADDR]
scratch[write, $temp_scratch0, temp_scratch_addr, 0, 4], ctx_swap[scratch_sig]
.end
*/ .endif
NULL#:
next_packet#:
br[ReceiveNextPacket#] // loop around and wait for next packet
sequence_error#:
.begin
.reg $temp_scratch temp_scratch_addr
immed[$temp_scratch, SEQUENCE_ERROR]
immed[temp_scratch_addr, SCRATCH_MSG_ADDR]
scratch[write, $temp_scratch, temp_scratch_addr, 0, 1], ctx_swap[scratch_sig]
ctx_arb[kill]
.end
size_error#:
.begin
.reg $temp_scratch temp_scratch_addr
immed[$temp_scratch, INCORRECT_SIZE]
immed[temp_scratch_addr, SCRATCH_MSG_ADDR]
scratch[write, $temp_scratch, temp_scratch_addr, 0, 1], ctx_swap[scratch_sig]
ctx_arb[kill]
.end
rec_error#:
.begin
.reg $temp_scratch temp_scratch_addr
immed[$temp_scratch, RECEIVE_ERROR]
immed[temp_scratch_addr, SCRATCH_MSG_ADDR]
scratch[write, $temp_scratch, temp_scratch_addr, 0, 1], ctx_swap[scratch_sig]
ctx_arb[kill]
.end
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