?? sys_loopback_bw_3_in_rx.uc
字號:
/* line_rate_bw_in_rx.uc
*
*
*
* NOTE: THIS IS NOT A PERFORMANCE BENCHMARK!!!! IT IS JUST TO CHECK IF THE
* HARDWARE IS ABLE TO HANDLE DATA AT THE LINERATE THAT IS BEING
* PUMPED INTO THE SYSTEM
*
*---------------------------------------------------------------------------
*
* I N T E L P R O P R I E T A R Y
*
* COPYRIGHT (c) 2002 BY INTEL CORPORATION. ALL RIGHTS
* RESERVED. NO PART OF THIS PROGRAM OR PUBLICATION MAY
* BE REPRODUCED, TRANSMITTED, TRANSCRIBED, STORED IN A
* RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER
* LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,
* MAGNETIC, OPTICAL, CHEMICAL, MANUAL, OR OTHERWISE, WITHOUT
* THE PRIOR WRITTEN PERMISSION OF :
*
* INTEL CORPORATION
*
* 2200 MISSION COLLEGE BLVD
*
* SANTA CLARA, CALIFORNIA 95052-8119
*
*---------------------------------------------------------------------------
*
*
* system: IXDP2400
* subsystem: DIAG
* author: dalsraja, November 11, 2002
* revisions:
*
*
* --------------------------------------------------------------------------
*/
#include "common_uc.h"
#include "sys_loopback_bw_3.h"
#define RX_TRANSFER_THREAD &$TransferReg00
#define RX_SIGNAL &rx_sig
#define NEXT_CTX_SIGNAL_NUM IN_SAME_ME_SIG_NUM
#define NEXT_CTX_SIG_DATA ((1 << 7) | (NEXT_CTX_SIGNAL_NUM << 3))
.reg cur_me cur_ctx
.reg same_me_sig_info
.reg sram_channel_number t0
.reg ring
.reg RxConfigData
.reg $TransferReg00 $TransferReg01
.reg RBuf_Base Rbuf_Elem_Done Rx_Thd_Freelist
.reg null elem bytecnt rx_port_num
//.reg error sopbit eopbit
.reg $sr0
.reg $ring_data
.reg @sramDescBase @dramPacketBase
.sig rx_sig same_me_sig inter_me_sig
.sig scratch_sig sram_sig dram_sig
.xfer_order $TransferReg00 $TransferReg01
.set $TransferReg00
.set_sig inter_me_sig
.addr same_me_sig IN_SAME_ME_SIG_NUM
.addr inter_me_sig IN_INTER_ME_SIG_NUM
// *****************************************
// Get current ME and ctx info
// *****************************************
.begin
.reg temp
local_csr_rd[ACTIVE_CTX_STS]
immed[temp, 0]
alu[cur_me, 0x1F, AND, temp, >>3] // Extract the current ME number
alu[cur_ctx, 0x7, AND, temp] // Extract the current context number
.end
.if (cur_me == 0)
immed[Rx_Thd_Freelist, RX_THREAD_FREELIST_0]
.elif (cur_me == 1)
immed[Rx_Thd_Freelist, RX_THREAD_FREELIST_1]
.elif (cur_me == 2)
immed[Rx_Thd_Freelist, RX_THREAD_FREELIST_2]
.else
immed[Rx_Thd_Freelist, RX_THREAD_FREELIST_3]
.endif
freelist_addr_done#:
immed[ring, (RING_0 << 2)] // ring number in a register
alu[sram_channel_number, --, B, CHAN_NUMBER, <<SRAM_CHANNEL_NUMBER_FIELD]
alu[t0, sram_channel_number, OR, Q_NUMBER, <<SRAM_Q_ARRAY_NUMBER_FIELD]
immed[RBuf_Base, RBUF_TBUF ]
immed[Rbuf_Elem_Done, RBUF_ELEMENT_DONE]
// immed[same_me_sig_info, NEXT_CTX_SIG_DATA]
.if (cur_ctx == 0)
immed[same_me_sig_info, (1 | (NEXT_CTX_SIGNAL_NUM << 3))]
// .elif (cur_ctx == 1)
// immed[same_me_sig_info, (0 | (NEXT_CTX_SIGNAL_NUM << 3))]
.else
// immed[same_me_sig_info, 0] // Just to avoid warning
ctx_arb[kill]
.endif
.begin
.reg RxThreadList
immed[RxThreadList, (RX_SIGNAL << 12)]
alu[RxThreadList, RxThreadList, OR, cur_me, <<7]
alu[RxThreadList, RxThreadList, OR, cur_ctx, <<4]
alu[RxConfigData, RxThreadList, OR , RX_TRANSFER_THREAD]
alu[RxConfigData, --, B, RxConfigData, <<16] // Shift 16 for msf[fast_wr...]
.end
ctx_arb[voluntary] // Swap out and let next ctx complete the init
br!=ctx[0, init_done#]
// *****************************************
// Initialisation by ctx 0 of each ME
// *****************************************
init_thread0_only#:
immed[@sramDescBase, (IN_SRAM_DESC_BASE & MASK_16BIT)]
immed_w1[@sramDescBase, ((IN_SRAM_DESC_BASE >> 16) & MASK_16BIT)]
immed[@dramPacketBase, (IN_DRAM_PCKT_BASE & MASK_16BIT)]
immed_w1[@dramPacketBase, ((IN_DRAM_PCKT_BASE >> 16) & MASK_16BIT)]
wait_for_inter_me_sig#:
br_!signal[inter_me_sig, wait_for_inter_me_sig#]
init_done#:
.set_sig same_me_sig
br=ctx[0, StartReceive#] // If ctx 0, branch to label to start start receiving
ctx_arb[same_me_sig]
StartReceive#:
ReceiveNextPacket#:
.set_sig rx_sig same_me_sig
// local_csr_wr[SAME_ME_SIGNAL, same_me_sig_info]
msf[fast_wr, --, Rx_Thd_Freelist, RxConfigData] // add thread to freelist
// ctx_arb[rx_sig, same_me_sig]
ctx_arb[rx_sig]
// RSW should be in xfer register
// Transfer RBUF data to sram_in transfer registers
//***************************************
// Extract RSW
//***************************************
RSW#:
alu[null, 0x1, AND, $TransferReg00, >>9] // Extract null
bne[NULL#] // If null=1, result=0
// alu[error, 0x1, AND, $TransferReg00, >>13] // Extract error
.set_sig same_me_sig
// local_csr_wr[SAME_ME_SIGNAL, same_me_sig_info]
sram[dequeue, $sr0, t0, 0], sig_done[sram_sig] // Get a buffer from the queue
alu[elem, --, B, $TransferReg00, >>24] // RBUF element number
// alu[sopbit, 0x1, AND, $TransferReg00, >>15] // Check SOP
// alu[eopbit, 0x1, AND, $TransferReg00, >>14] // Check EOP
alu[bytecnt, 0xFF, AND, $TransferReg00, >>16] // Extract byte count
alu[rx_port_num, 0xF, AND, $TransferReg00] // Extract channel info
.begin
.reg refcnt ind_ref_data
//****************************************************
// Calculate the reference count for dram[rbuf_rd...]
//****************************************************
alu[refcnt, --, B, bytecnt, >>3]
alu[--, bytecnt, AND, 0x7]
bne[set_refcnt_overwrite_bit#]
alu[refcnt, refcnt, -, 1]
set_refcnt_overwrite_bit#:
alu[refcnt, refcnt, OR, 1, <<4] // Set the overwrite bit for refcnt
.local RBufOffset
alu[RBufOffset, --, B, elem, <<IN_RBUF_ADDR_SHF]
alu[ind_ref_data, RBuf_Base, +, RBufOffset]
.endlocal // RBufOffset
// ctx_arb[sram_sig, same_me_sig], defer[1]
ctx_arb[sram_sig], defer[1]
alu[ind_ref_data, (1 << 4), OR, ind_ref_data, <<5] // shift rbuf addr and set the overwrite bit
.set_sig same_me_sig
// local_csr_wr[SAME_ME_SIGNAL, same_me_sig_info]
.local pkt_buff_addr rel freebuffer bdptr ring_data $sram_data
//*************************************************************
// Calculate packet buffer address where packet will be stored
//*************************************************************
alu[freebuffer, --, B, $sr0, <<2] // Shift 2 as address obtained is longword address
alu[rel, freebuffer, -, @sramDescBase]
alu[rel, --, B, rel, <<5]
alu[pkt_buff_addr, @dramPacketBase, +, rel]
//****************************************************
// Move from RBUF to DRAM
//****************************************************
alu[ind_ref_data, ind_ref_data, OR, refcnt, <<21] // shift refcnt and add for indirect ref
dram[rbuf_rd, --, pkt_buff_addr, 0, 8], indirect_ref, sig_done[dram_sig]
//****************************************************
// Put packet info in SRAM
//****************************************************
alu[$sram_data, rx_port_num, OR, bytecnt, <<4]
sram[write, $sram_data, freebuffer, sram_channel_number, 1], sig_done[sram_sig]
//****************************************************
// Put buffer address in scratch ring
//****************************************************
alu[$ring_data, --, B, freebuffer]
check_ring_full#:
br_inp_state[SCR_Ring0_Full, check_ring_full#]
scratch[put, $ring_data, ring, 0, 1], sig_done[scratch_sig]
// ctx_arb[sram_sig, dram_sig, scratch_sig, same_me_sig]//, defer[1]
ctx_arb[sram_sig, dram_sig, scratch_sig]
.endlocal // pkt_buff_addr
.end
// .set_sig same_me_sig
// local_csr_wr[SAME_ME_SIGNAL, same_me_sig_info]
//**************************************************************
// Free up Element by writing to RBUF_Element_Done
//**************************************************************
.begin
.reg rbuf_elem_done_data
alu[rbuf_elem_done_data, --, B, elem, <<16]
msf[fast_wr, --, rbuf_elem_done_data, RBUF_ELEMENT_DONE]
.end
// ctx_arb[scratch_sig, same_me_sig]
NULL#:
next_packet#:
br[ReceiveNextPacket#] // loop around and wait for next packet
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