?? emi_bw_rx.uc
字號:
/* emi_bw_rx.uc
*
* Brief:
*
*
*---------------------------------------------------------------------------
*
* I N T E L P R O P R I E T A R Y
*
* COPYRIGHT (c) 2002 BY INTEL CORPORATION. ALL RIGHTS
* RESERVED. NO PART OF THIS PROGRAM OR PUBLICATION MAY
* BE REPRODUCED, TRANSMITTED, TRANSCRIBED, STORED IN A
* RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER
* LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,
* MAGNETIC, OPTICAL, CHEMICAL, MANUAL, OR OTHERWISE, WITHOUT
* THE PRIOR WRITTEN PERMISSION OF :
*
* INTEL CORPORATION
*
* 2200 MISSION COLLEGE BLVD
*
* SANTA CLARA, CALIFORNIA 95052-8119
*
*---------------------------------------------------------------------------
*
*
* system: IXDP2400
* subsystem: DIAG
* author: dalsraja, 30 October, 2002
* revisions:
*
*
* --------------------------------------------------------------------------
*/
#include "common_uc.h"
#define RX_SINGLE_PHY MSF_SINGLE_PHY
#define RX_WIDTH MSF_WIDTH_4x8
#define RX_ENABLE_MASK 0xF
#define RX_MODE MSF_POS_UTOPIA
#define RX_ELEMENTSIZE MSF_ELEMENTSIZE_128
#define RBUF_ELEM_COUNT (1 << (7 - RX_ELEMENTSIZE))
#define RBUF_ADDR_SHF (6 + RX_ELEMENTSIZE)
#define RX_ELEMENT_SIZE_BYTE (1 << RBUF_ADDR_SHF)
#define RX_TRANSFER_THREAD &$TransferReg00
#define RX_SIGNAL_THREAD &rx_sig_thd
#define MESSAGING_ADDR 0x1000
#define DRAM_PCKT_BASE 0x1000000
#define INTER_ME_SIG_NUM 15
#define SIG_THD_NUM 0
#define ME_0 0
#define ME_1 1
#define ME_2 2
#define ME_3 3
.reg cur_me
.reg $TransferReg00 $TransferReg01
.reg RxThreadList bytecnt elem error expected_sequence mask
.reg RxConfigData $RxConfigData0 RxConfigData0
.reg rbuf
.reg MsfAddress Thd_Freelist_Addr Rbuf_Elem_Done
.reg dramPacketBase
.reg $rbuf_data0 $rbuf_data1
.reg $failure_type $scratch_data
.sig msf_sig sig_dram_xfer1
.sig rx_sig_thd inter_me_sig
.xfer_order $TransferReg00 $TransferReg01
.xfer_order $rbuf_data0 $rbuf_data1
.xfer_order $failure_type $scratch_data
.addr inter_me_sig INTER_ME_SIG_NUM
.set $TransferReg00
.set_sig inter_me_sig
br=ctx[0, Init_Value#]
ctx_arb[kill]
Init_Value#:
.begin
.reg temp
local_csr_rd[ACTIVE_CTX_STS]
immed[temp, 0]
alu[cur_me, 0x1F, AND, temp, >>3] // Extract the current ME number
.end
.if (cur_me == 0)
immed[Thd_Freelist_Addr, RX_THREAD_FREELIST_0]
.elif (cur_me == 1)
immed[Thd_Freelist_Addr, RX_THREAD_FREELIST_1]
.elif (cur_me == 2)
immed[Thd_Freelist_Addr, RX_THREAD_FREELIST_2]
.else
immed[Thd_Freelist_Addr, RX_THREAD_FREELIST_3]
.endif
immed[Rbuf_Elem_Done, RBUF_ELEMENT_DONE]
immed[rbuf, RBUF_TBUF]
immed[RxThreadList, ((RX_SIGNAL_THREAD << 12) | (0 << 4))]
alu[RxThreadList, RxThreadList, OR, cur_me, <<7]
alu[RxConfigData, RxThreadList, OR, RX_TRANSFER_THREAD]
alu[RxConfigData, --, B, RxConfigData, <<16]
immed[expected_sequence, 0]
immed[mask, MASK_4BIT]
alu[--, cur_me, -, 0]
beq[init_msf#]
ctx_arb[inter_me_sig]
br[ReceivePacket#]
init_msf#:
//****************************************************
// Configure RX/TX Control
//****************************************************
immed[RxConfigData0, ((0<<9) | (RX_ELEMENTSIZE << 2))]
immed_w1[RxConfigData0, ((RX_MODE << 6) | (RX_WIDTH << 4) | (RX_SINGLE_PHY << 3) | (0<<1)|(0<<0))]
alu[$RxConfigData0, --, B, RxConfigData0]
immed[MsfAddress, MSF_RX_CONTROL]
msf[write, $RxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]
//******************************************************
// Initialize RBUF Freelist to add elements to the list
//******************************************************
.begin
.reg temp_reg temp
immed[temp_reg, 0]
init_RBUF#:
alu[temp, --, B, temp_reg, <<16]
msf[fast_wr, --, temp, RBUF_ELEMENT_DONE]
alu[temp_reg, temp_reg, +, 1]
alu[--, RBUF_ELEM_COUNT, -, temp_reg]
bne[init_RBUF#]
.end
//******************************************************
// Configure RX UP Control CSRs
//******************************************************
.begin
.reg RxUPControl0
immed[RxUPControl0, (UP_CTRL_PP_MODE | UP_CTRL_CP_MODE | UP_CTRL_PARITY | UP_CTRL_CELLSIZE | UP_CTRL_DRTIME)]
alu[$RxConfigData0, --, B, RxUPControl0]
immed[MsfAddress, RX_UP_CONTROL_0]
msf[write, $RxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]
immed[MsfAddress, RX_UP_CONTROL_1]
msf[write, $RxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]
immed[MsfAddress, RX_UP_CONTROL_2]
msf[write, $RxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]
immed[MsfAddress, RX_UP_CONTROL_3]
msf[write, $RxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]
.end
//****************************************************
// Configure RX/TX Control
//****************************************************
immed[RxConfigData0, ((0<<9) | (RX_ELEMENTSIZE << 2))]
immed_w1[RxConfigData0, ((RX_ENABLE_MASK << 12) | (RX_MODE << 6) | (RX_WIDTH << 4) | (RX_SINGLE_PHY << 3) | (0<<1)|(0<<0))]
alu[$RxConfigData0, --, B, RxConfigData0]
immed[MsfAddress, MSF_RX_CONTROL]
msf[write, $RxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]
.begin
.reg temp
immed[temp, ((ME_1 << 7) | (SIG_THD_NUM << 4) | (INTER_ME_SIG_NUM << 0))]
alu[--, --, B, temp]
cap[fast_wr, ALU, interthread_sig]
immed[temp, ((ME_2 << 7) | (SIG_THD_NUM << 4) | (INTER_ME_SIG_NUM << 0))]
alu[--, --, B, temp]
cap[fast_wr, ALU, interthread_sig]
immed[temp, ((ME_3 << 7) | (SIG_THD_NUM << 4) | (INTER_ME_SIG_NUM << 0))]
alu[--, --, B, temp]
cap[fast_wr, ALU, interthread_sig]
.end
//********************************************************
// Start of Test
//********************************************************
ReceivePacket#:
.set_sig rx_sig_thd
msf[fast_wr, --, Thd_Freelist_Addr, RxConfigData] // add thread to freelist
ctx_arb[rx_sig_thd]
// RSW should be in xfer register
// Transfer RBUF data to sram_in transfer registers
//***************************************
// Extract RSW
//****************************************
RSW#:
alu[elem, --, B, $TransferReg00, >>24] // Get element number
alu[bytecnt, 0xFF, AND, $TransferReg00, >>16] // Extract byte count
alu[error, 0xF, AND, $TransferReg00, >>10] // Extract error information
.if (error > 0)
immed[$failure_type, RECEIVE_ERROR]
alu[$scratch_data, --, B, $TransferReg00]
br[rbuf_to_dram#]
.endif
//*************************************
// Transfer from RBUF to xfer register
//*************************************
no_error#:
.begin
.reg rbuf_addr
alu[rbuf_addr, rbuf, OR, elem, <<7]
msf[read, $rbuf_data0, rbuf_addr, 0, 1], ctx_swap[msf_sig]
.end
.begin
.reg cur_sequence temp
alu[cur_sequence, --, B, $rbuf_data0, >>24]
alu[--, expected_sequence, -, cur_sequence]
beq[sequence_good#]
immed[$failure_type, SEQUENCE_ERROR]
alu[$scratch_data, expected_sequence, OR, cur_sequence, <<16]
// alu[$scratch_data, --, B, $rbuf_data0]
.end
rbuf_to_dram#:
//*********************************
// Transfer from RBUF to DRAM
//*********************************
.begin
.reg pkt_buff_addr rel refcnt temp dramPacketBase
immed[dramPacketBase, (DRAM_PCKT_BASE & MASK_16BIT)]
immed_w1[dramPacketBase, ((DRAM_PCKT_BASE >> 16) & MASK_16BIT)]
alu[refcnt, --, B, bytecnt, >>3]
alu[--, bytecnt, AND, 0x7]
beq[cont1#]
alu[refcnt, refcnt, +, 1]
alu[refcnt, refcnt, OR, 1, <<4] // Set the overwrite bit for refcnt
cont1#:
alu[temp, rbuf, OR, elem, <<7] // 128B
alu[temp, 16, OR, temp, <<5] // shift rbuf addr and set the overwrite bit
alu[temp, temp, OR, refcnt, <<21] // shift refcnt and add for indirect ref
dram[rbuf_rd, --, dramPacketBase, 0, 8], indirect_ref, sig_done[sig_dram_xfer1]
ctx_arb[sig_dram_xfer1]
.end
br[error_handling#]
//**************************************************************
// Free up Element by writing to RBUF_Element_Done
//**************************************************************
sequence_good#:
.begin
.reg temp
alu[temp, --, B, elem, <<16]
msf[fast_wr, --, temp, RBUF_ELEMENT_DONE]
.end
alu[expected_sequence, expected_sequence, +, 1]
alu[expected_sequence, mask, AND, expected_sequence]
br[ReceivePacket#]
//**************************************************************
// If an error occurs, write to XScale to indicate failure
//**************************************************************
error_handling#:
.begin
.reg scratch_addr
.sig scratch_sig
immed[scratch_addr, MESSAGING_ADDR]
scratch[write, $failure_type, scratch_addr, 0, 2], ctx_swap[scratch_sig]
.end
ctx_arb[kill]
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