?? sys_loopback_bw_3_eg_tx.uc
字號:
/* emi_bw_tx.uc
*
* Brief:
*
*
*---------------------------------------------------------------------------
*
* I N T E L P R O P R I E T A R Y
*
* COPYRIGHT (c) 2002 BY INTEL CORPORATION. ALL RIGHTS
* RESERVED. NO PART OF THIS PROGRAM OR PUBLICATION MAY
* BE REPRODUCED, TRANSMITTED, TRANSCRIBED, STORED IN A
* RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER
* LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,
* MAGNETIC, OPTICAL, CHEMICAL, MANUAL, OR OTHERWISE, WITHOUT
* THE PRIOR WRITTEN PERMISSION OF :
*
* INTEL CORPORATION
*
* 2200 MISSION COLLEGE BLVD
*
* SANTA CLARA, CALIFORNIA 95052-8119
*
*---------------------------------------------------------------------------
*
*
* system: IXDP2400
* subsystem: DIAG
* author: dalsraja, 23 December, 2002
* revisions:
*
*
* --------------------------------------------------------------------------
*/
#include "common_uc.h"
#define TX_ELEMENT_SIZE MSF_ELEMENTSIZE_128
#define TX_ENABLE_MASK 0xF
#define TX_MODE MSF_POS_UTOPIA
#define TX_WIDTH MSF_WIDTH_4x8
#define TX_SINGLE_PHY MSF_SINGLE_PHY
#define TBUF_ELEM_COUNT (1 << (7 - TX_ELEMENT_SIZE))
#define TBUF_ELEM_COUNT_PER_PORT (TBUF_ELEM_COUNT >> 2)
#define TBUF_ADDR_SHF (6 + TX_ELEMENT_SIZE)
#define TX_ELEMENTSIZE_BYTE (1 << TBUF_ADDR_SHF)
#define TBUF_ELEM_COUNT_4PORT TBUF_ELEM_COUNT_PER_PORT
#define TBUF_ELEM_COUNT_4PORT_MASK (TBUF_ELEM_COUNT_4PORT - 1)
#define TX_CONTROL_EOP (1 << 8)
#define TX_CONTROL_SOP (1 << 9)
#define POS_PAYLOAD_LENGTH 48
#define FUTURE_COUNT_SIG_NUM &future_count_sig
#define FUTURE_COUNT_STEP 22
#define FUTURE_COUNT_STEP_ADDR 0x1600
#define LOOP_COUNT_ADDR 0x1604
#define BURST_COUNT_ADDR 0x1608
#define XSCALE_MSG_ADDR 0x1610
#define INTER_ME_SIG_NUM 15
#define NUMBER_OF_PORTS 4
#define ME_0 0
#define ME_1 1
#define ME_2 2
#define ME_3 3
#define PORT_0 0
#define PORT_1 1
#define PORT_2 2
#define PORT_3 3
#define SIG_THD_NUM 0
.reg cur_me
.reg MsfAddress TxSequenceAddr
.reg pkt_in_one_burst pkt_in_cur_burst
.reg total_loop cur_loop
.reg future_count_value future_count_incr
.reg byte_count
.reg $misc_ctrl_val
.reg TxConfigData0
.reg $TxConfigData0
.reg $TxControlWord0 $TxControlWord1
.reg tbuf_element base_element_for_port
.sig msf_sig future_count_sig inter_me_sig cap_sig
.xfer_order $TxControlWord0 $TxControlWord1
.addr inter_me_sig INTER_ME_SIG_NUM
.set_sig inter_me_sig
br=ctx[0, init#]
ctx_arb[kill]
init#:
.begin
.reg temp
local_csr_rd[ACTIVE_CTX_STS]
immed[temp, 0]
alu[cur_me, 0x1F, AND, temp, >>3] // Extract the current ME number
.end
// immed[total_packets_tx, 0]
immed[tbuf_element, 0]
immed[byte_count, POS_PAYLOAD_LENGTH]
immed[cur_loop, 0]
immed[future_count_incr, FUTURE_COUNT_STEP]
/*
.begin
.reg temp_scratch_addr $temp_scratch_data
.sig scratch_sig
immed[temp_scratch_addr, FUTURE_COUNT_STEP_ADDR]
scratch[read, $temp_scratch_data, temp_scratch_addr, 0, 1], ctx_swap[scratch_sig]
alu[future_count_incr, --, B, $temp_scratch_data]
.end
*/
.begin
.reg temp_scratch_addr $temp_scratch_data
.sig scratch_sig
immed[temp_scratch_addr, LOOP_COUNT_ADDR]
scratch[read, $temp_scratch_data, temp_scratch_addr, 0, 1], ctx_swap[scratch_sig]
alu[total_loop, --, B, $temp_scratch_data]
.end
.begin
.reg temp_scratch_addr $temp_scratch_data
.sig scratch_sig
immed[temp_scratch_addr, BURST_COUNT_ADDR]
scratch[read, $temp_scratch_data, temp_scratch_addr, 0, 1], ctx_swap[scratch_sig]
alu[pkt_in_one_burst, --, B, $temp_scratch_data]
.end
.if (cur_me == 0)
immed[base_element_for_port, (TBUF_ELEM_COUNT_PER_PORT * PORT_0)]
immed[TxSequenceAddr, TX_SEQUENCE_0]
.elif (cur_me == 1)
// ctx_arb[kill]
immed[base_element_for_port, (TBUF_ELEM_COUNT_PER_PORT * PORT_1)]
immed[TxSequenceAddr, TX_SEQUENCE_1]
.elif (cur_me == 2)
// ctx_arb[kill]
immed[base_element_for_port, (TBUF_ELEM_COUNT_PER_PORT * PORT_2)]
immed[TxSequenceAddr, TX_SEQUENCE_2]
.else
// ctx_arb[kill]
immed[base_element_for_port, (TBUF_ELEM_COUNT_PER_PORT * PORT_3)]
immed[TxSequenceAddr, TX_SEQUENCE_3]
.endif
alu[--, cur_me, -, 0]
beq[init_msf#]
ctx_arb[inter_me_sig]
br[msf_init_done#]
init_msf#:
//****************************************************
// Configure TX Control
//****************************************************
immed[MsfAddress, MSF_TX_CONTROL]
immed[TxConfigData0, (TX_ELEMENT_SIZE << 2)] // put control and data into diff freelist
immed_w1[TxConfigData0, ((TX_ENABLE_MASK << 8) | (TX_MODE << 6) | (TX_WIDTH << 4) | (TX_SINGLE_PHY << 3) | (0<<1)|(0<<0))]
alu[$TxConfigData0, --, B, TxConfigData0]
msf[write, $TxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]
immed[MsfAddress, TX_UP_CONTROL_0]
immed[TxConfigData0, (UP_CTRL_CP_MODE | UP_CTRL_PARITY | UP_CTRL_CELLSIZE | UP_CTRL_DRTIME)]
alu[$TxConfigData0, --, B, TxConfigData0]
msf[write, $TxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]
immed[MsfAddress, TX_UP_CONTROL_1]
msf[write, $TxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]
immed[MsfAddress, TX_UP_CONTROL_2]
msf[write, $TxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]
immed[MsfAddress, TX_UP_CONTROL_3]
msf[write, $TxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]
immed[MsfAddress, MSF_TX_CONTROL]
immed[TxConfigData0, (TX_ELEMENT_SIZE << 2)] // put control and data into diff freelist
immed_w1[TxConfigData0, ((TX_ENABLE_MASK << 12) | (TX_ENABLE_MASK << 8) | (TX_MODE << 6) | (TX_WIDTH << 4) | (TX_SINGLE_PHY << 3) | (0<<1)|(0<<0))]
alu[$TxConfigData0, --, B, TxConfigData0]
msf[write, $TxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]
.begin
.reg temp
immed[temp, ((ME_1 << 7) | (SIG_THD_NUM << 4) | (INTER_ME_SIG_NUM << 0))]
alu[--, --, B, temp]
cap[fast_wr, ALU, interthread_sig]
immed[temp, ((ME_2 << 7) | (SIG_THD_NUM << 4) | (INTER_ME_SIG_NUM << 0))]
alu[--, --, B, temp]
cap[fast_wr, ALU, interthread_sig]
immed[temp, ((ME_3 << 7) | (SIG_THD_NUM << 4) | (INTER_ME_SIG_NUM << 0))]
alu[--, --, B, temp]
cap[fast_wr, ALU, interthread_sig]
.end
msf_init_done#:
cap[read, $misc_ctrl_val, MISC_CONTROL], ctx_swap[cap_sig] // Read the MISC_CONTROL reg
next_burst#:
//****************************************************
// Configure the TIMESTAMP registers and configure
// the FUTURE_COUNT_SIGNAL register
//****************************************************
immed[pkt_in_cur_burst, 0]
immed[future_count_value, 0]
local_csr_wr[TIMESTAMP_LOW, 0]
local_csr_wr[TIMESTAMP_HIGH, 0]
local_csr_wr[CSR_CTX_POINTER, 0]
local_csr_wr[INDIRECT_FUTURE_COUNT_SIGNAL, FUTURE_COUNT_SIG_NUM]
alu[--, $misc_ctrl_val, OR, 1, <<7] // Set the timestamp enable bit
cap[fast_wr, alu, MISC_CONTROL] // and write to the MISC_CONTROL register
next_packet#:
local_csr_wr[CSR_CTX_POINTER, 0]
alu[future_count_value, future_count_value, +, future_count_incr]
alu[future_count_value, 0, +16, future_count_value]
local_csr_wr[INDIRECT_CTX_FUTURE_COUNT, future_count_value]
//*******************************************************
// Read the Transmit Sequence
//*******************************************************
.begin
.reg result tmp_val tmp_tbuf $TxSequenceData
read_tx_sequence_loop#:
msf[read, $TxSequenceData, TxSequenceAddr, 0, 1], ctx_swap[msf_sig]
alu[result, TBUF_ELEM_COUNT_4PORT_MASK, AND, $TxSequenceData] // get mpkts actually sent
alu[tmp_val, TBUF_ELEM_COUNT_4PORT_MASK, AND, tbuf_element]
alu[--, tmp_val, -, result]
bge[cont_comp_tbuf_tx_sequnce#], defer[1]
alu[tmp_tbuf, --, b, tmp_val]
alu[tmp_tbuf, tmp_tbuf, +, TBUF_ELEM_COUNT_4PORT] // wrap around, add tbuf element number
cont_comp_tbuf_tx_sequnce#:
alu[result, tmp_tbuf, -, result] // compare with totals in tbuf
alu[--, result, -, 8] // compare with threshold
bge[read_tx_sequence_loop#] // loop again
.end //result tmp_tbuf
.set_sig future_count_sig
//*******************************************************
// Write the Transmit Control Word with appropriate data
//*******************************************************
.begin
.reg temp cur_tbuf_elem
alu[cur_tbuf_elem, base_element_for_port, +, tbuf_element]
immed[MsfAddress, TBUF_ELEMENT_CONTROL_V]
alu[MsfAddress, MsfAddress, OR, cur_tbuf_elem, <<3]
immed[temp, (TX_CONTROL_SOP | TX_CONTROL_EOP)]
alu[$TxControlWord0, temp, OR, byte_count, <<24]
immed[$TxControlWord1, 0]
ctx_arb[future_count_sig]
msf[write, $TxControlWord0, MsfAddress, 0, 2], sig_done[msf_sig]
.end
alu[tbuf_element, tbuf_element, +, 1]
alu[tbuf_element, tbuf_element, AND, (TBUF_ELEM_COUNT_PER_PORT - 1)]
alu[pkt_in_cur_burst, pkt_in_cur_burst, +, 1]
.begin
.reg $temp_reg_val temp_mask
.reg temp_scratch_addr $temp_scratch_data
.sig scratch_sig
.if (pkt_in_cur_burst == pkt_in_one_burst)
alu[$temp_reg_val, --, B, $misc_ctrl_val] // Set the timestamp disable bit
cap[write, $temp_reg_val, MISC_CONTROL], sig_done[cap_sig] // and write to the MISC_CONTROL register
.if (total_loop > 0)
alu[cur_loop, cur_loop, +, 1]
// .if (cur_loop == total_loop)
// ctx_arb[kill]
// .endif
.endif
ctx_arb[msf_sig, cap_sig]
immed[temp_scratch_addr, XSCALE_MSG_ADDR]
alu[temp_scratch_addr, temp_scratch_addr, OR, cur_me, <<2]
immed[$temp_scratch_data, 0xFFFF]
wait_for_xscale#:
scratch[test_and_clr, $temp_scratch_data, temp_scratch_addr, 0], sig_done[scratch_sig]
ctx_arb[scratch_sig]
alu[--, --, B, $temp_scratch_data]
beq[wait_for_xscale#]
br[next_burst#]
.else
ctx_arb[msf_sig]
.endif
.end
br[next_packet#]?? 快捷鍵說明
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